Motorola MVME5100 ECC Control Register

3-46 Computer Group Literature Center Web Site
System Memory Controller (SMC)
3
ECC Control Register
refdis When set, refdis causes the refresher and all o f its
associated counters and state machines to be cleared and
maintained that way until refdis is removed (cleared). If a
refresh cycle is in process when refdis is updated by a
write to this register, the update does not take effect until
the refresh cycle has completed. This prev e nts the
generation of illegal cycles to the SDRAM when refdis is
updated.
rwcb rwcb, when set, causes reads and writes to SDRAM from
the PPC60x bus to access check-bit data rather than
normal data. The data path used for reading and writing
check bits is D0-D7. Each 8-bit check-bit location
services 64 bits of normal data. Figure 3-10 shows the
relationship between normal data and check-bit data.
Address $FEF80028
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
0 0 0 0 0 refdis rwcb derc 0 0 0 apien scien dpien sien mien
int
0 0 0 0 0 0 0 mbe_me
Operation
R R R R R R/W R/W R/W R R R R/W R/W R/W R/W R/W
R/C
READ ZERO
R R R R R R R R/W
Reset
X X X X X 0 PL 0 PL 1 PL X X X 0PL 0 PL 0 PL 0 PL 0PL
0PL
X X X X X X X 0 PL