Functional Description
http://www.motorola.com/computer/literature 3-23
3
I2C Byte Write
The I2C Status Register contains the i2_cmplt bit which is used to indicate
if the I2C master controller is ready to perform an operation. Therefore, the
first step in the programming sequence shoul d be to test the i2_cmplt bit
for the operation-complete status. The nex t step is to initiate a start
sequence by first setting the i2 start and i2 enbl bits in the I2C Control
Register and then writing the device address (bits 7-1) and write bit (bit
0=0) to the I2C Transmitter Data Register. The i2_cmplt bit will be
automatically clear with the write cycle to th e I2C Transmitter Data
Register. The I2C Status Register must now be polled to test the i2_cmplt
and i2_ackin bits. The i2_cmplt bit becomes set when the device address
and write bit have been transmitted, and the i2_ackin bit provides status as
to whether or not a slave device acknowledged the device address. With
the successful transmission of the device address, the word address will be
loaded into the I2C Transmitter Data Register to be transmitte d to the slave
device. Again, i2_cmplt and i2_ackin bits must be tested for proper
response. After the word address is succ essfully transmitted, the next data
loaded into the I2C Transmitter Data Register will be transferred to the
address location selected previously within the slave device. After
i2_cmplt and i2_ackin bits have been tested for proper response, a stop
sequence must be transmitted to the slave device by first setting the i2 stop
and i2enbl bits in the I2C Control Register and then writing a dummy data
(data=don’t care) to the I2C Transmitter Data Register. The I2C Status
Register must now be polled to test i2_cmplt bit for the operation-complete
status. The stop sequence will initiate a progr amming cycle for the serial
EEPROM and also relinquish the ASIC master’s possession of the I2C bus.
Figure 3-5 shows the suggested software flow diagram for programming
the I2C byte write operation.