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System Memory Controller (SMC)
3
Notes 1. All empty bit fields are reserved and read as zeros.
2. All status bits are shown in italics.
3. All control bits are shown with underline.
4. All control-and-status bits are shown with italics and
underline.
Detailed Register Bit Descriptions
The following sections describe the registers and their bits in detail. The
possible operations for each bit in the register set are as follows:
R The bit is a read only status bit.
R/W The bit is readable and writable.
R/C The bit is cleared by writing a one to itself.
The possible states of the bits after lo cal and power-up reset are as defined
below.
P The bit is affected by power-up reset (PURST_).
L The bit is affected by local reset (RST_).
X The bit is not affected by reset.
V The effect of reset on the bit is variable.