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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
The WDTxCNTL register will always become unarmed after the second write regardless of byte lane selection. Reads may be performed at any time from the WDTxCNTL register and will not affect the write armi ng sequence The following example displays the PPCBug commands, which arm, the disarm, the Watchdog timer 2.Table 2-14. WDTxCNTL Programming
Byte Lane Selection Results
KEY ENAB
/RES RELOAD WDT WDTxCNTL Register
0:7 8:15 16:23 24:31 Prescaler /
Enable Counter RES/ENAB RELOAD
No x x x No Change No Change No Change No Change
Yes No x x Update
from
RES/ENAB
Update
from
RELOAD
No Change No Change
Yes Yes No x Update
from data
bus
Update
from
RELOAD
Update
from data
bus
No Change
Yes Yes x No Update
from data
bus
Update
from
RELOAD
Update
from data
bus
No Change
Yes Yes Yes Yes Update
from data
bus
Update
from data
bus
Update
from data
bus
Update
from
data bus