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System Memory Controller (SMC)
3
The following sections describe the logical function of the SMC. The SMC
has interfaces between the PowerPC bus and SDRAM, ROM/Flash, and its
Control and Status Register sets (CSR).
SDRAM Accesses
Four-beat Reads/Writes
The SMC performs best when doing bursting (4-beat accesses). This is
made possible by the burst nature of synchronous DRAMs. When the
PPC60x Master begins a burst read to SDRAM, the SMC starts the access
and when the access time is reached, the SDRAM provides all four beats
of data, one on each clock. Hence, the SMC can provide the four beats of
data with zero idle clocks between each beat.
Single-beat Reads/Writes
Because of start-up, addressing, and completion overhead, single-beat
accesses to and from the PPC60x bus do not achieve data rates as high as
do four-beat accesses. Single-beat writes are the slowest because they
require that the SMC perform a read cycle then a write cycle to the
SDRAM in order to complete. Fortunately, in most PPC60x systems,
single-beat accesses can be held to a minimum, especially with d ata cache
and copyback modes in place.
Address Pipelining
The SMC takes advantage of the fact that PPC60x processors can do
address pipelining. Many times while a data cycle is finishing, the PPC60x
processor begins a new address cycle. The SMC can begin the next
SDRAM access earlier when this happens, thus increasing throughput.