2-110 Computer Group Literature Center Web Site
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
The following conventions are used in the Hawk register charts:
❏R - Read Only field.
❏R/W - Read/Write field.
❏S - Writing a ONE to this field sets this field.
❏C - Writing a ONE to this field clears this field.
MPIC Registers
The MPIC register map is shown in Table 2-19. The "Off" field is the
address offset from the base address of the MPIC registers in the PPC-IO
or PPC-Memory space. Note that this map does not depict linear
addressing. The PCI-SLAVE of the PHB has two decoders for generating
the MPIC select. These decoders will generate a select and acknowledge
all accesses which are in a reserved 256K byte range. If the index into that
256K block does not decode a valid MPIC register address, the logic will
return $00000000.
The registers are 8, 16, or 32 bits accessible.
Table 2-19. MPIC Register Map
3
13
02
92
82
72
62
52
42
32
22
12
01
91
81
71
61
51
41
31
21
11
09876543210Off
FEATURE REPORTING REGISTER 0 $01000
GLOBAL CONFIGURATION REGISTER 0 $01020
MPIC VENDOR IDENTIFICATION REGISTER $01080
PROCESSOR INIT REGISTER $01090
IPI0 VECTOR-PRIORITY REGISTER $010a0
IPI1 VECTOR-PRIORITY REGISTER $010b0
IPI2 VECTOR-PRIORITY REGISTER $010c0
IPI3 VECTOR-PRIORITY REGISTER $010d0