2-82 Computer Group Literature Center Web Site
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
PPC Error Status Register
The Error Status Register (ESTAT) provides an array of status bits
pertaining to the various errors that the PHB can detect. The bits withi n the
ESTAT are defined in the following paragraphs.
OVF Error Status Overflow. This bit is set when any error is
detected and any of the error status bits are already set. It
may be cleared by writing a 1 to it; writing a 0 to it has no
effect.
XBTO PPC Address Bus Time-out. This bit is set when the PPC
timer times out. It may be cleared by writing a 1 to it;
writing a 0 to it has no effect. When the XBTOM bit in the
EENAB register is set, the assertion of this bit will assert
MCHK to the master designated by the XID field in the
EATTR register. When the XBTOI bit in the EENAB
register is set, the assertion of this bit will ass ert an
interrupt through the MPIC.
XDPE PPC Data Parity Error. This bit is set when the PHB
detects a data bus parity error. It may be cleared by writing
a 1 to it; writing a 0 to it has no effect. When the XDPEM
bit in the EENAB register is set, the assertion of this bit
will assert MCHK to the master designated by the XID
field in the EATTR register. When the XDPEI bit in the
EENAB register is set, the assertion of this bit will assert
an interrupt through the MPIC.
Address $FEFF0024
Bit 01234567891
01
11
21
31
41
51
61
71
81
92
02
12
22
32
42
52
62
72
82
93
03
1
Name ESTAT
OVF
XBTO
XDPE
PPER
PSER
PSMA
PRTA
Operation R R R
R/C
R
R/C
R
R/C
R/C
R/C
R/C
Reset $00 $00 $00
0
0
0
0
0
0
0
0