Registers
http://www.motorola.com/computer/literature 2-127
2
Current Task Priority Registers
There is one Task Priority Register per pro cessor. Priority levels from 0
(lowest) to 15 (highest) are supported. Setting the Task Priority Register to
15 masks all interrupts to this processor. Ha rdware will set the task register
to $F when it is reset or when the Init bit associated with this processor is
written to a one.
TP Task Priority of processor.
Interrupt Acknowledge Registers
On PowerPC-based systems, Interrupt Acknowledge is implemented as a
read request to a memory-mapped Interrupt Acknowledge register.
Reading the Interrupt Acknowledge register returns the interrupt vector
corresponding to the highest priority pending interrupt. Reading this
register also has the following side effects. Reading this register wit hout a
pending interrupt will return a value of $FF hex.
❏The associated bit in the Interrupt Pending Register is cleared.
❏Reading this register will update the In-Servi ce register.
VECTOR Vector. This vector is returned when the Interrupt
Acknowledge register is read.
Offset Processor 0 $20080
Processor 1 $21080
Bit 3
13
02
92
82
72
62
52
42
32
22
12
01
91
81
71
61
51
41
31
21
11
09876543210
Name CURRENT TASK PRIORITY
TP
Operation RRRRR/W
Reset $00 $00 $00 $0 $F
Offset Processor 0 $200A0
Processor 1 $210A0
Bit 3
13
02
92
82
72
62
52
42
32
22
12
01
91
81
71
61
51
41
31
21
11
09876543210
Name VECTOR
Operation RRRR
Reset $00 $00 $00 $FF