Index
IN-10 Computer Group Literature Center Web Site
I
N
D
E
X
SDRAM Enable and Size Register 3-41,
3-67
SDRAM Speed Attributes Register 3-69
Vendor/Device Register 3-39
SMC Data Parity Error Address Register
3-62
SMC Data Parity Error Log Register 3-61
SMC Data Parity Error Lower Data Register
3-63
SMC External Register Set 3-73
SMC Scrub Address Register 3-53
SMC tben Register 3-74
soft reset
MPIC 4-5
software considerations 3-75
Hawk 3-75
Software Readable Header Register 1-29
sources of reset
MVME5100 4-5
SPD 3-77
SPD JEDEC standard definition 1-12
Speculative PCI Request 2-47
spread I/O addressing
as function of PHB 2-30
Spurious Vector Register 2-118
SRAM base address 3-35
status bit descriptions 3-38
Status Register 1-23, 1-24
strap pins configuration for the
PC87308VUL 1-34
swen 3-52
syndrome codes ordered by bit in error 3-87
System Bus 1-8
System Controller Mode bit 1-24
System Memory Controller (SMC) 3-1
T
TA as used with PPC Slave 2-7
Table 2-10
Table 2-2. 2-10
target initiated termination
2-24
TBEN Bit Register 1-27
tben Register
SMC 3-74
Timer Basecount Registers 2-120
Timer Current Count Registers 2-119
Timer Destination Registers 2-122
Timer Frequency Register 2-118
Timer Vector/Priority Registers 2-121
timing (ROM/Flash access) 3-19
transaction(s)
burst 2-8
compelled 2-7
instance of interrupt 2-8
ordering 2-48
PCI originated/PPC bound described 2-5
posted 2-7
PPC originated/PCI bound described 2-4
transactions
PPC Slave limits 2-8
unable to retry 2-8
transfer types
generated by PPC Master 2-14
PCI command code dependent 2-14
PPC60x bus 2-14
triple- (or greater) bit error 3-12
Tundra Universe Controller 1-2
U
Universe ASIC 1-17
Universe chip problems after a PCI reset 4-5
Universe VMEbus interface ASIC 1-8, 1-15
User configuration Data 1-13
V
Vendor ID/ Device ID Registers 2-98
Vendor ID/Device ID Registers 2-70
Vendor Identification Register 2-116
Vendor/Device Register
SMC 3-39
Vital Product Data 1-10, 1-13
Vital Product Data (VPD) B-1