xi
Spurious Vector Register.........................................................................2-118
Timer Frequency Register.......................................................................2-118
Timer Current Count Registers................................................................2-119
Timer Basecount Registers......................................................................2-120
Timer Vector/Priority Registers..............................................................2-121
Timer Destination Registers....................................................................2-122
External Source Vector/Priority Registers..............................................2-122
External Source Destination Registers....................................................2-124
Hawk Internal Error Interrupt Vector/Priority Register..........................2-125
Hawk Internal Error Interrupt Destination Register................................2-126
Interprocessor Interrupt Dispatch Registers............................................2-126
Current Task Priority Registers...............................................................2-127
Interrupt Acknowledge Registers............................................................2-127
End-of-Interrupt Registers.......................................................................2-128
CHAPTER 3 System Memory Controller (SMC)
Introduction................................................................................................................3-1
Overview.............................................................................................................3-1
Bit Ordering Convention....................................................................................3-1
Features...............................................................................................................3-1
Block Diagrams.........................................................................................................3-2
Functional Description...............................................................................................3-6
SDRAM Accesses...............................................................................................3-6
Four-beat Reads/Writes...............................................................................3-6
Single-beat Reads/Writes............................................................................3-6
Address Pipelining.......................................................................................3-6
Page Holding...............................................................................................3-7
SDRAM Speeds...........................................................................................3-7
SDRAM Organization........................................................................................3-9
PPC60x Bus Interface.........................................................................................3-9
Responding to Address Transfers................................................................3-9
Completing Data Transfers..........................................................................3-9
PPC60x Data Parity...................................................................................3-10
PPC60x Address Parity.............................................................................3-10
Cache Coherency.......................................................................................3-11
Cache Coherency Restrictions...................................................................3-11
L2 Cache Support......................................................................................3-11
SDRAM ECC...................................................................................................3-11
Cycle Types...............................................................................................3-11
Error Reporting..........................................................................................3-12