Programming Model
http://www.motorola.com/computer/literature 3-65
3
i2_stop When set, the I2C master controller generates a stop sequence
on the I2C bus on the next dummy write (data=don’t care) to
the I2C Transmitter Data Register and clears the i2_cmplt bit
in the I2C Status Register. After the stop sequence has been
transmitted, the I2C master controller will au tomatically clear
the i2_stop bit and then set the i2_cmplt bit in the I2C Status
Register.
i2_ackout When set, the I2C master controller generates an acknowledge
on the I2C bus during read cycles. This bit should be used only
in the I2C sequential read operation and must remain cleared
for all other I2C operations. For I2C sequential read operation,
this bit should be set for every single byte received except o n
the last byte in which case it should be cleared.
i2_enbl When set, the I2C master interface will be enabled for I2C
operations. If clear, reads and writes to all I2C registers are
still allowed but no I2C bus operations will be performed.
I2C Status Register
i2_datin This bit is set whenever the I2C master controller has
successfully received a byte of read data from an I2C bus slave
device. This bit is cleared after the I2C Receiver Data Register
is read.
i2_err This bit is set when both i2_start and i2_stop bits in the I2C
Control Register are set at the same time. T h e I2C master
controller will then clear the contents of t he I2C Control
Address $FEF800A0
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
0
0
0
0
i2_datin
i2_err
i2_ackin
i2_cmplt
Operation READ ZERO READ ZERO READ ZERO
R
R
R
R
R
R
R
R
Reset XXX
X
X
X
X
0 PL
0 PL
0 PL
1 PL