Motorola MVME5100 I2C Receiver Data Register

Programming Model
http://www.motorola.com/computer/literature 3-67
3
I2C Receiver Data Register
I2_DATARD The I2_DATARD contains the receive byte for I2C data
transfers. During I2C sequential read operation, the current
receive byte must be read before any new one can be brough in.
A read of this register will automatically cl ear the i2_datin bit in
the I2C Status Register.
SDRAM Enable and Size Register (Blocks E,F,G,H)
Writes to this register must be enveloped by a period of time in which no
accesses to SDRAM occur. The requirements of the envelope are that all
SDRAM accesses must have completed before the write starts and none
should begin until after the write is done. A simple way to do this is to
perform at least two read accesses to this or another register before and
after the write.
Additionally, sometime during the enve lo pe, before or after the write, all
of the SDRAMs’ open pages must be closed and the Hawk’s open page
tracker reset. The way to do this is to allow en o ugh time for at least one
SDRAM refresh to occur by waiting for the 32-bit Counter (see section
further on) to increment at least 100 times. T h e wait period needs to
happen during the envelope.
Address $FEF800B0
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name I2_DATARD
Operation READ ZERO READ ZERO READ ZERO READ
Reset XXX0 PL
Address $FEF800C0
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
ram e en 0 0 0 ram e siz0 ram e siz1 ram e siz2 ram e siz3 ram f en 0 0 0 ram f siz0 ram f siz1 ram f siz2 ram f siz3 ram g en 0 0 0 ram g siz0 ram g siz1 ram g siz2 ram g siz3 ram h en 0 0 0 ram h siz0 ram h siz1 ram h siz2 ram h siz3
Operation
R/W
R R R R/W R/W R/W R/W
R/W
R R R R/W R/W R/W R/W
R/W
R R R R/W R/W R/W R/W
R/W
R R R R/W R/W R/W R/W
Reset
0 PL X X X 0 P 0 P 0 P 0 P 0 PL X X X 0 P 0 P 0 P 0 P 0 PL X X X 0 P 0 P 0 P 0 P 0 PL X X X 0 P 0 P 0 P 0 P