Motorola MVME5100 Summary of Changes, Overview of Contents

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Summary of Changes
The following changes were made for the 2nd revision of this manual.
Overview of Contents
The following paragraphs briefly describe the contents of each chapter.
Chapter 1, Product Data and Memory Maps, provides a description of the
MVME5100, tables of specific memory maps and other control registers.
Chapter 2, Hawk PCI Host Bridge & Multi-Processor Interrupt
Controller, provides a description of the Hawk’s PowerPC to Local Bus
Bridge (PHB) and the Multi-Processor Interru pt Controller (MPIC)
including a list of features, a block diagram, a functional description and
corresponding register tables.
Chapter 3, System Memory Controller (SMC), provides an explanation of
the System Memory Controller (SMC) portion of the Hawk ASIC
including a features list, block diagrams, functional descriptions, and an
explanation and description of all corresponding registers.
Chapter 4, Hawk Programming Details, procides a summary of the Hawk
programming details that are relevant to every day programming
functions, including a listing of the Hawk MPIC External Interrupts, the
Date Doc. Rev Changes
09/2001 V5100A/PG2 Memory Maps and additional register information
was added to Chapter 1. Corrections were made to
Table 4-1 in Chapter 4. Additions were made to
Appendix A, Releated Documentation. Appendix
B, VPD Information was added. This section titled
"About this Manual" was also added.
07/2003 v5100A/PG3 Added information at the end of Chapter 1 on
IPMC7xx ISA Bus Resources. Corrected incorrect
address for DS1621 SROM. Added Appendix C,
VMEbus Mapping Example. Added
corrections/additions for CLK_FREQUENCY
Register in Chapter 3.