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System Memory Controller (SMC)
3
rom_a_rv is initialized at po w er-up reset to match the
value on the RD0 pin.
rom a en When rom a en is set, accesses to Block A ROM/Fl ash in
the address range selected by ROM A BASE are enabled.
When rom a en is cleared, they are disabled.
rom a we When rom a we is set, writes to Block A ROM/Flash are
enabled. When rom a we is cleared, they are disabled.
Note that if rom_a_64 is cleared, only 1-byte writes are
allowed. If rom_a_64 is set, only 4-byte writes are
allowed. The SMC ignores other writes. If a valid write is
attempted and rom a we is cleared, the write does not
happen but the cycle is terminated normally.
See Table 3-13 for details of ROM/Flash accesses.
Table 3-13. Read/Write to ROM/Flash
Cycle Trans fer
Size Alignment rom_x_64 rom_x_we Hawk Response
write 1-byte X 0 0 Normal termination, but no
write to ROM/Flash
write 1-byte X 0 1 Normal termination, write
occurs to ROM/Flash
write 1-byte X 1 X No Response
write 4-byte Misaligned X X No Response
write 4-byte Aligned 0 X No Response
write 4-byte Aligned 1 0 Normal termination, but no
write to ROM/Flash
write 4-byte Aligned 1 1 Normal termination, write
occurs to ROM/Flash
write 2,3,5,6,7,
8,32-byte XXXNo Response
readXXXXNormal Termination