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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
Architectural Overview
A functional block diagram of the Hawk’s PCI Host Bridge (PHB) is
shown in Figure 2-1. The PHB control logic is subdivided into the
following functions: PCI Slave, PCI Master, PPC Slave and PPC Master.
The PHB data path logic is subdivided into the following functions: PCI
FIFO, PPC FIFO, PCI Input, PPC Input, PCI Output, and PPC Output.
Address decoding is handled in the PCI Decode and PPC Decode blocks.
The control register logic is contained in the PCI Registers and PPC
Registers blocks. The clock phasing and reset control logic is contained
within the PPC/PCI Clock block.
The FIFO structure implemented within PH B was selected to allow
independent data transfer operations to occur between PCI bound
transactions and PPC bound transactions. The PCI FIFO is used to support
PPC bound transactions, while the PPC FIFO is used to support PCI bound
transactions. Each FIFO supports a command path and a data path. The
data path portion of each FIFO incorporates a multiplexer to allow
selection between write data and read data, as well as logic to handle the
PPC/PCI endian function.
All PPC originated PCI bound transactions utilize the PPC Slave and PCI
Master functions for maintaining bus tracking and control. During both
write and read transactions, the PPC Slave places command information
into the PPC FIFO. The PCI Master draws this command information from
the PPC FIFO when it is ready to process the t ransaction. During write
transactions, write data is captured from the PPC60x bus within the PPC
Input block. This data is fed into the PPC FIFO. The PCI Output block
removes the data from the FIFO and p resents it to the PCI bus. During rea d
transactions, read data is captured from the PCI bus within the PCI Input
block. From there, the data is fed into the PPC FIFO. The PPC Output
block removes the data from the FIFO and presents it to the PPC60x bus.