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System Memory Controller (SMC)
3
Error ReportingThe SMC checks data from the SDRAM during single- and four-beat reads, during single-beat writes, and during scrubs. Table 3-2 shows the actions it takes for different errors during these accesses 60x.Note that the SMC does not assert TEA_ on double-bit errors. In fact, the SMC does not have a TEA_ signal pin and it assumes that the system does not implement TEA_. The SMC can, however, assert machine check (MCHK0_) on double-bit error. Table 3-2. Error Reporting

Error Type Single-Beat/Four-

Beat Read Single-Beat Write Four-Beat Write Scrub

Single-Bit

Error

Terminate the
PPC60x bus cycle nor-
mally.
Provide corrected data to
the PPC60x bus master.
Assert Hawk’s internal
error interrupt, if so
enabled. 2
Terminate the
PPC60x bus cycle nor-
mally.
Correct the data read
from SDRAM, merge
with the write data, and
write the corrected,
merged data to SDRAM.
Assert Hawk’s internal
error interrupt, if so
enabled. 2
N/A 1
This cycle is not seen on
the PPC60x bus.
Write corrected data
back to SDRAM if so
enabled.
Assert Hawk’s internal
error interrupt, if so
enabled. 2

Double-Bit

Error

Terminate the
PPC60x bus cycle nor-
mally.
Provide miss-corrected,
raw SDRAM data to the
PPC60x60x bus master.
Assert Hawk’s internal
error interrupt, if so
enabled. 2
Assert MCHK0_ if so
enabled.
Terminate the
PPC60x bus cycle nor-
mally.
Do not perform the write
portion of the read-mod-
ify-write cycle to
SDRAM.
Assert Hawk’s internal
error interrupt, if so
enabled. 2
Assert MCHK0_ if so
enabled.
N/A 1
This cycle is not seen on
the PPC60x bus.
Do not perform the
write portion of the
read-modify-write cycle
to SDRAM.
Assert Hawk’s internal
error interrupt if so
enabled. 2

Triple- (or

greater)

Bit Error

Some of these errors are detected correctly and are treated the same as double-bit errors. The rest could
show up as “no error” or “single-bit error”, both of which are inco rre ct.