55 If you have not already created a Compare file for the previous test (single-clock,
single-edge state acquisition, page 3-31), use the following steps to create one. For
subsequent passes through this test, skip this step and go to step 6.
aPress Run. The display should show a checkerboard pattern of alternating As and 5s.
Verify the pattern by scrolling through the display.
bPress the List key. In the pop up menu, use the RPG knob to move the cursor to
Compare. Press Select.
cIn the Compare menu, move the cursor to Copy Listing to Reference, then select
Execute from the pop-up menu and press the Select key.
dMove the cursor to Specify Stop Measurement and press the Select key. Press Select
again to turn on Compare. At the pop up menu, select Compare. Move the cursor to
the Equal field and press the Select key. At the pop up menu, select Not Equal. Press
Done.
eMove the cursor to the Reference Listing field and select. The field should toggle to
Difference Listing.
6Press the blue shift key, then press the Run key. If 2 - 4 acquisitions are obtained
without the "Stop Condition Satisfied" message appearing, then the test passes.
Press Stop to halt the acquisition. Record the Pass or Fail results in the
performance test record.
7Enable the pulse generator channel 2 COMP (with the LED on).
8Check the clock pulse width.
aEnable the pulse generator channel 1 and channel 2 outputs (with the LED off).
bb In the oscilloscope Timebase menu, select Delay. Using the oscilloscope knob,
position the clock waveform so that the waveform is centered on the screen.
cIn the oscilloscope Delta V menu, set the Marker 1 Position to Chan 2, then set
Marker 1 at −1.3000 V. Set the Marker 2 Position to Chan 2, then set Marker 2 at
−1.3000 V.
dIn the oscilloscope Delta T menu, select Start On Neg Edge 1. Select Stop On Pos
Edge 1.
eIf the pulse width is outside of the limits, adjust the pulse generator channel 2 width
and select the oscilloscope Precision Edge Find until the pulse width is within limits.
Testing Performance
To test the multiple-clock, multiple-edge, state acquisition
3–42