11 Press the blue shift key, then press the Run key. If 2 - 4 acquisitions are obtained
without the "Stop Condition Satisfied" message appearing, then the test passes.
Press Stop to halt the acquisition. Record the Pass or Fail results in the
performance test record.
12 Test the next setup/hold combination.
aIn the logic analyzer Format menu, select Master Clock.
bTurn off and disconnect the clocks just tested.
cRepeat steps 1 through 12 for the next setup/hold combination listed in step 1 on
page 3-40, until all listed setup/hold combinations have been tested.
When aligning the data and clock waveforms using the oscilloscope, align the waveforms
according to the setup time of the setup/hold combination being tested, +0.0 ps or −100 ps.
hen continue through the complete test.
Testing Performance
To test the multiple-clock, multiple-edge, state acquisition
3–44