ARM ARM DUI 0224I manual Lists the clock signals

Hardware Description

Table 3-5 lists the clock signals.

Table 3-5 ARM926EJ-S PXP Development Chip clocks

Clock signal	Frequency	Description		Source
GLOBALCLK	6–75MHz	This is a master clock that is shared between the FPGA, Logic Tile,		ICS307
		and ARM926EJ-S PXP Development Chip.		OSC0
HCLKM1	6–50MHz	The AHB master interface clock is used by the AHB Bridge 1 to		ICS307
		off-chip peripherals when it operates in asynchronous mode. By		OSC1
		default, the multiplexor selects GLOBALCLK (driven by OSC0)
		as the external clock source.
			Note
		By default, the AHB M1, AHB M2, and AHB S bridges all operate
		in synchronous mode and the external reference clocks are ignored.
HCLKM2	6–40MHz	The AHB master interface clock is used by the AHB Bridge 2 to		ICS307
		off-chip peripherals when it operates in asynchronous mode. By		OSC2
		default, the multiplexor selects GLOBALCLK (driven by OSC0)
		as the external clock source.
HCLKS	6–33MHz	The AHB master interface clock is used by the AHB Bridge to		ICS307
		on-chip peripherals when it operates in asynchronous mode. By		OSC3
		default, the multiplexor selects GLOBALCLK (driven by OSC0)
		as the external clock source.
PLLCLKEXT	6–200MHz	When the development chip PLL is not used, this input can be used		ICS307
		to drive the CPU and AMBA clocks. This clock is selected by the		OSC0
		Clock and Reset Controller which is controlled by the System
		Controller.
			Note
		By default, the ARM926EJ-S PXP Development Chip uses a PLL
		to generate the CPU and AMBA clocks based on the
		XTALCLKEXT signal. PLLCLKEXT and REFCLK32K are
		not used.
REFCLK32K	32.768kHz	This clock is selected by the Clock and Reset Controller which is		Crystal
	(fixed)	controlled by the System Controller. This signal is also used to
		generate a 1Hz clock for the Real Time Clock. When the
		development chip PLL is not used, this input can be used to drive
		the CPU and AMBA clocks.

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