ARM ARM DUI 0224I ADDR15 NCS0 ADDR16, ADDR17, Nirq, ADDR18, Nwen, ADDR19, Noen, ADDR20, ADDR21

			Memory Expansion Boards
	Table E-6 Static memory connector signals (continued)
Pin No.	Signal	Pin No.	Signal
95	ADDR[15]	96	nCS[0]
97	ADDR[16]	98	nBUSY, Indicates that memory is
			not ready to be released from reset.
			If LOW, this signal holds nRESET
			active.
99	ADDR[17]	100	nIRQ
101	ADDR[18]	102	nWEN
103	ADDR[19]	104	nOEN
105	ADDR[20]	106	nBLS[3], Byte Lane Select for bits
			[31:24]
107	ADDR[21]	108	nBLS[2], Byte Lane Select for bits
			[23:16]
109	ADDR[22]	110	nBLS[1], Byte Lane Select for bits
			[15:8]
111	ADDR[23]	111	nBLS[0], Byte Lane Select for bits
			[7:0]
113	ADDR[24]	114	CSWIDTH[0], Indicates bus width
			for fitted part. Do not route through
			stackable boards.
115	ADDR[25]	116	CSWIDTH[1], Indicates bus width
			for fitted part. Do not route through
			stackable boards.
117	ADDRVALID, Indicates that the	118	CLK[1]
	address output is stable during
	synchronous burst transfers
119	BAA, Burst Address Advance. Used	120	CLK[0]
	to advance the address count in the
	memory device

a. VDDIO is the data voltage to host. Do not route through on stackable boards

ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved. E-19