ARM ARM DUI 0224I - page 369

Memory Expansion Boards
ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved. E-19
95 ADDR[15] 96 nCS[0]
97 ADDR[16] 98 nBUSY, Indicates that memory is
not ready to be released from reset.
If LOW, this signal holds nRESET
active.
99 ADDR[17] 100 nIRQ
101 ADDR[18] 102 nWEN
103 ADDR[19] 104 nOEN
105 ADDR[20] 106 nBLS[3], Byte Lane Select for bits
[31:24]
107 ADDR[21] 108 nBLS[2], Byte Lane Select for bits
[23:16]
109 ADDR[22] 110 nBLS[1], Byte Lane Select for bits
[15:8]
111 ADDR[23] 111 nBLS[0], Byte Lane Select for bits
[7:0]
113 ADDR[24] 114 CSWIDTH[0], Indicates bus width
for fitted part. Do not route through
stackable boards.
115 ADDR[25] 116 CSWIDTH[1], Indicates bus width
for fitted part. Do not route through
stackable boards.
117 ADDRVALID, Indicates that the
address output is stable during
synchronous burst transfers
118 CLK[1]
119 BAA, Burst Address Advance. Used
to advance the address count in the
memory device
120 CLK[0]
a. VDDI O is the data voltage to host. Do not route through on stackable boards
TableE-6 Static memory connector signals (continued)
Pin No. Signal Pin No. Signal