ARM ARM DUI 0224I manual Npbreset, Npbsdcreconfig, Npllreset, Nporeset, Npowerfail, PnRST, PnTRST

Hardware Description

			Table 3-4 Reset signal descriptions (continued)
Name	Function
nPBRESET	Push-button reset signal to the FPGA. The signal is generated by pressing the reset
	button.
nPBSDCRECONFIG	This signal is generated from the DEV CHIP CONFIG pushbutton and causes a
	reconfiguration of the ARM926EJ-S PXP Development Chip.
nPLLRESET	Reset for ARM926EJ-S PXP Development Chip PLL clock circuit.
nPORESET	Power-on reset to development chip, configuration flash, and expansion memory. The
	CPU core, all system peripherals, and all system controller registers are reset. For
	details on system registers reset at different reset levels, see Table 4-4 on page 4-18.
nPOWERFAIL	This signal shuts down the onboard regulators. It is triggered by the supply voltage
	falling to less than 9V. (The signal is only valid if the DC IN supply is used.)
		Note
	There is a nPWRFAIL signal to the interrupt controller, but this signal is not affected
	by the power supply voltage. nPWRFAIL can, however, be used to test automatic
	shutdown code (see Miscellaneous System Control Register, SYS_MISC on
	page 4-36).
P_nRST	System reset from PCI backplane.
P_nTRST	JTAG TRST signal from PCI backplane.
		Note
	There is a separate JTAG connector and an independent scan chain on the PCI
	backplane. The JTAG chain on the PB926EJ-S does not normally extend to the PCI
	expansion backplane. There is a separate JTAG connector on the PCI backplane for
	configuring devices on the backplane and on installed PCI cards. There are also links
	that can be fitted to the PB926EJ-S that connects the two JTAG chains together, but
	these links are normally only fitted for manufacturing tests.
nPWRFAIL	This signal is provided by the FPGA to the interrupt controller. User software can test
	this signal and shut down before a power loss causes a loss of data.
		Note
	This signal is not driven by any power-detection logic. It is provided so that custom
	implementations of the FPGA image have a signal that could be manipulated by a
	register. Creating such an FPGA image would enable testing of user software that
	implements a shutdown routine.

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