ARM ARM DUI 0224I 4.16 MultiPort Memory Controller, MPMC

Programmer’s Reference

4.16 MultiPort Memory Controller, MPMC

The Multiport Memory Controller (MPMC) is an AMBA compliant SoC peripheral that

is developed, tested, and licensed by ARM Limited.

The MPMC controls the dynamic memory on the PB926EJ-S. SyncFlash is supported

on the dynamic memory bus but it cannot be selected as boot memory.

For information on default values for the memory controllers, see Memory

characteristics on page 4-15. Sample programs that configure and use dynamic

memory can be found on the CD that accompanies the PB926EJ-S.

4.16.1 Register values

Table4-47 on page 4 -72 lists the register values for typical operation with 133MHz

SDRAM. The HCLK frequency is 70MHz and the SDRAM is organized as four banks

of 8MB x 16bit.

Note

The platform.a library contains memory setup routines. See Building an application

with the platform library on page 2-23.

Table4-46 MPMC implementation

Property Value

Location ARM926EJ-S PXP Development Chip.

Memory base address

0x10110000

Interrupt NA.

DMA The MPMC does not use interrupts or DMA. DMA transfers,

however, can be set up to access memory controlled by the

MPMC.

Release version ARM MPMC GX175 r0p0-00alp2.

Reference documentation ARM PrimeCell Multiport Memory Controller (GX175)

Technical Reference Manual (see also Memory interface on

page 3-15) .