ARM ARM DUI 0224I manual Where it can be used as the CPU clock for low-power mode

	Hardware Description
RTC	There is an external real-time clock clocked by a dedicated 32kHz crystal
	oscillator. The RTC outputs the 32kHz clock to the FPGA where it is
	buffered and then sent to the ARM926EJ-S PXP Development Chip
	where it can be used as the CPU clock for low-power mode.
Ethernet	The Ethernet controller has a 25MHz dedicated crystal oscillator for
	timing the Ethernet bus. HCLKM2 (typically generated from the
	programmable oscillator OSC0) is used as a reference frequency for the
	controller interface to the FPGA.
USB	The 24MHz reference from the programmable oscillator OSC0 is used as
	a reference frequency for the external USB controller.
Logic Tile	A Logic Tile can be connected to the expansion connectors. The tile
	normally uses the GLOBALCLK from the PB926EJ-S as the clock for
	its AHB buses. The tile can, however, also generate GLOBALCLK.
	(The signal nGLOBALCLKEN from Z50 on the Logic Tile indicates to
	the PB926EJ-S whether GLOBALCLK is supplied from OSC0 or from
	the Logic Tile. This signal is pulled HIGH by the Logic Tile to select the
	Logic Tile GLOBALCLK as the source for GLOBALCLK on the
	PB926EJ-S.)
	The tile can also generate the external clocks for the AHB bridges when
	they are operating in asynchronous mode. In normal operation, the AHB
	bridges operate in synchronous mode and the PB926EJ-S is the source of
	the bridge clocks connected to the tile.
	The static memory clocks, CLCD data clock, and several of the
	peripheral clocks from the PB926EJ-S are connected to the tile.
Debug	The JTAG connector supplies the reference JTAG clock TCK. There is
	also an on-board USB debug port that is driven by the 24MHz reference
	and a dedicated 6MHz crystal oscillator.

The various clocks and clock selection mechanism are described in the following sections:

•ARM926EJ-S PXP Development Chip clocks on page 3-39

•ICS307 programmable clock generators on page 3-48

•Peripheral clocks on page 3-54

•RealView Logic Tile clocks on page 3-52.

Note

The clocking selection and control logic in the PB926EJ-S enables you to emulate many different clock systems and operating modes (for example, low-power mode with slow clocks, operation without a PLL, and synchronous or asynchronous AHB bridges).

ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved. 3-37