Hardware Description
3-42 Copyright © 2003-2010 ARM Limited. All rights reserved. ARM DUI 0224I

Figure 3-19 Default clock sources and frequencies

CFGHCLKDIVSEL[1:0]
ARM926EJ-S Dev. Chip
CFGDATA values
XTALCLKEXT (35MHz)
SDRAM
HDATAM1
HDATAM 2
On-chip
peripherals
CFGMBXCLKDIVSEL[1:0]
MBX
clock
divider
(2)
SMC
clock
divider
(2)
Flash
CFGSMCCLKDIVSEL[1:0]
HCLK
divider
(3)
HCLKEXT
divider
(2)
CFGHCLKEXTDIVSEL[2:0]
PLL
ARM926EJ-S
CPUCLK
(210MHz)
SYS_OSCx registers and
serializer ICS307 control signals
SYS_CFGDATA0
SYS_CFGDATA1
FPGA
OSCCLK0
(35MHz)
OSC0
AHB
M1
bridge
AHB
M2
bridge
AHB
S
bridge
MPMC
HCLKEXT (35MHz)
HCLK (70MHz)
MBX
(35MHz)
35MHz
70MHz
External AHB clock 35MHz
(all bridges operating in
synchronous mode)
Internal AHB
clock 70MHz
24MHz
crystal
HCLKCTRL[7:0]
GLOBALCLK
Clock multiplexors (equivalent circuit)
FPGA AHB
clocks 35MHz
GLOBALCLK
(to FPGA logic)
PLL used with
XTALCLKEXT to
generate HCLKEXT
and HCLK
GLOBALCLK
HCLKM1_F2L
HCLKM2_F2L
HCLKS_F2L
(To RealView
Logic Tile)