ARM ARM DUI 0224I manual Pci, 2GB, Sic

Programmer’s Reference

Table 4-1 Memory map (continued)

Peripheral		Location	Interrupta PIC	Address	Region
			and SIC		size
PCI interface bus windows		PCI	PCI3: PIC 30,	0x41000000–	752MB
PCI SelfCfg window:	0x41000000		SIC 30 PCI2:	0x6FFFFFFF
PCI Cfg window:	0x42000000		PIC 29, SIC 29
PCI I/O window:	0x43000000		PCI1: PIC 28,
PCI memory window 0: 0x44000000			SIC 28 PCI0:
PCI memory window 1: 0x50000000			PIC 27, SIC 27
PCI memory window 2: 0x60000000
MPMC Chip Selects 2–3, expansion dynamic memory		Expansion	-	0x70000000–	256MB
		memory		0x7FFFFFFF
RealView Logic Tile expansion ( AHB M1 bus). (If a		Board	PIC 21–PIC30	0x80000000–	2GB
RealView Logic Tile is installed, accesses in this range		(RealView	(shared with	0xFFFFFFFF
must be decoded by the tile. This is the recommended		Logic Tile	SIC)
address range for placing memory-mapped peripherals in		headers)
a RealView Logic Tile.)

a.The primary interrupt controller is in the ARM926EJ-S PXP Development Chip. The secondary controller is in the FPGA. See Primary interrupt controller on page 4-58 and Interrupt controllers on page 4-57.

Figure 4-1 on page 4-8 shows the ARM Data bus memory map. See AHB bridges and the bus matrix on page 3-10 for details on other buses in the ARM926EJ-S PXP Development Chip.

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