Programmer’s Reference
4-94 Copyright © 2003-2010 ARM Limited. All rights reserved. ARM DUI 0224I
+0x8c SMBWSTOENR4
0x1
Output Enable Assertion Delay 4
+0x90 SMBWSTWENR4
0x1
Write Enable Assertion Delay 4
+0x94 SMBCR4
0x303121
Control Register for memory bank 4
+0x9c SMBWSTBRDR4
0x1
Burst Read Wait state Control Reg 4
Table4-70 Register values for Spansion LV256 (continued)
Address Name of SSMC
register Value Description