ARM ARM DUI 0224I

Hardware Description

The JTAG path chosen depends on whether the system is in configuration mode or

debug mode. The CONFIG link controls the nCFGEN signal that is routed through the

PB926EJ-S and tile connectors. Figure 3-43 on page 3-101, Figure 3-44 on page 3-102,

and Figure 3-45 on page 3-103 show the JTAG signal routing.

DBGACK Debug acknowledge

(to JTAG equipment)

DBGACK indicates to the debugger that the processor core has

entered debug mode. It is provided for compatibility with

third-party JTAG equipment.

GLOBAL_DONE FPGA configured GLOBAL_DONE is an open-collector signal that indicates when

FPGA configuration is complete. Although this signal is not a JTAG

signal, it does affect nSRST. The GLOBAL_DONE signal is

routed between all RealView boards.

nRTCKEN Return TCK enable nRTCKEN is an active LOW signal driven by any tile that requires

RTCK to be routed back to the JTAG equipment. If nRTCKEN is

HIGH, the baseboard drives RTCK LOW. If nRTCKEN is LOW,

the baseboard drives the TCK signal back to the JTAG equipment.

Table3-25 JTAG related signals (continued)

Name Description Function