Hardware Description
3-68 Copyright © 2003-2010 ARM Limited. All rights reserved. ARM DUI 0224I
3.10 Ethernet interface
The Ethernet interface is implemented with a SMC LAN91C111 10/100 Ethernet
single-chip MAC and PHY. This is provided with a slave interface to the system bus by
the FPGA.
The internal registers of the LAN91C111 are memory-mapped onto the AHB M2 bus
and occupy 16 word locations at
0x10010000
.
The isolating RJ45 connector incorporates two network status LEDs. The function of
the LEDs can be set to indicate link, activity, transmit, receive, full duplex, or 10/100
selection. See the data sheet for the LAN91C111 for more details on programming the
registers.
The architecture of the Ethernet interface is shown in Figure 3-28.
Figure 3-28 Ethernet interface architecture
Table3-16 Ethernet signals
Signal Description
USBETHD[31:0] Data lines to USB and Ethernet controllers.
USBETHA[8:2] Address lines to USB and Ethernet controllers.
ETHA[15:13] Address lines to Ethernet controller.
ETHnBE[3:0] Byte-enable signals to Ethernet controller.
TPO+, TPO- Signal from controller to Ethernet interface.