ARM ARM DUI 0224I manual Memory map, Sdram, 4KB

Programmer’s Reference

4.1Memory map

The locations for memory, peripherals, and controllers are listed in Table 4-1 and ARM Data bus memory map on page 4-8.

There are multiple buses in the ARM926EJ-S PXP Development Chip. Not all of the buses can access all of the memory regions. See AHB bridges and the bus matrix on page 3-10 and the ARM926EJ-S Reference Manual for details on the bus matrix and bus accesses.

Note

The MOVE and VFP coprocessors are not memory-mapped peripherals so they do not appear in the memory map listed in Table 4-1. See the appropriate technical reference manual for more detail on these devices.

Table 4-1 Memory map

Peripheral	Location	Interrupta PIC	Address	Region
		and SIC		size
MPMC Chip Select 0. Normally the bottom 64MB of the	Board	-	0x00000000–	64MB
first bank of SDRAM (During boot remapping, this can be			0x03FFFFFF
NOR flash or memory on a RealView Logic Tile.)
MPMC Chip Select 0, top 64MB of the first bank of	Board	-	0x04000000–	64MB
SDRAM			0x07FFFFFF
MPMC Chip Select 1, dynamic expansion memory	Memory	-	0x08000000–	128MB
	expansion		0x0FFFFFFF
System registers	FPGA	-	0x10000000–	4KB
			0x10000FFF
PCI controller configuration registers	FPGA	-	0x10001000–	4KB
			0x10001FFF
Serial Bus Interface	FPGA	-	0x10002000–	4KB
			0x10002FFF
Secondary Interrupt Controller (SIC)	FPGA	PIC 31	0x10003000–	4KB
			0x10003FFF
Advanced Audio CODEC Interface	FPGA	PIC24, SIC 24	0x10004000–	4KB
			0x10004FFF

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