ARM ARM DUI 0224I

Hardware Description

Figure 3-10 FPGA reload sequence

Note

The configuration flash can hold four FPGA images. However, only one FPGA image

is provided.

The configuration flash is a separate device and not part of the user flash.

You can use a JTAG debugger or the Progcards utility to reprogram the PLDs, FPGA,

and flash if the PB926EJ-S is placed in configuration mode. See also JTAG and USB

debug port support on page 3-96.

The PB926EJ-S is supplied with the configuration PLD and flash image already

programmed. The information in this section is provided, however, in case of accidental

erasure of the configuration PLD or flash image.

Caution

You are advised not to reprogram these devices with any images other than those

provided by ARM Limited.

Program the configuration PLD as follows:

1. Connect an interface cable to either the JTAG or USB debug port.

2. Put the PB926EJ-S into configuration mode by fitting the CONFIG link J32 on

the board and powering-up.

Note

The CONFIG link is a switch on some board versions.

3. Start the JTAG application and autoconfigure.

GLOBAL_DONE

nSYSPOR

LOCAL_DONE

nTRST

7μs

Released by Logic Tiles

2.6μs