List of Tables

Table 3-14

Display interface signals

3-63

Table 3-15

DMA signals for external devices

3-67

Table 3-16

Ethernet signals

3-68

Table 3-17

MMC/SD interface signals

3-75

Table 3-18

MMC signals

3-78

Table 3-19

Serial bus addresses

3-80

Table 3-20

Serial bus signals

3-80

Table 3-21

Smart Card interface signals

3-83

Table 3-22

SSP signal descriptions

3-85

Table 3-23

Serial interface signal assignment

3-90

Table 3-24

USB interface signal assignment

3-93

Table 3-25

JTAG related signals

3-98

Table 4-1

Memory map

4-3

Table 4-2

Selecting the boot device

4-10

Table 4-3

Memory chip selects and address range

4-16

Table 4-4

Register map for system control registers

4-18

Table 4-5

ID Register, SYS_ID bit assignment

4-21

Table 4-6

Oscillator Register, SYS_OSCx bit assignment

4-23

Table 4-7

Lock Register, SYS_LOCK bit assignment

4-24

Table 4-8

Configuration register 1

4-26

Table 4-9

Configuration register 2

4-27

Table 4-10

Flag registers

4-30

Table 4-11

Reset level control

4-31

Table 4-12

MCI control

4-32

Table 4-13

Flash control

4-32

Table 4-14

SYS_CLCD register

4-33

Table 4-15

SYS_CLCDSER register

4-34

Table 4-16

BOOT configuration switches

4-35

Table 4-17

SYS_MISC

4-36

Table 4-18

DMA map registers

4-37

Table 4-19

SYS_DMAPSRx, DMA mapping register format

4-38

Table 4-20

Oscillator test registers

4-40

Table 4-21

AHB monitor implementation

4-41

Table 4-22

AACI implementation

4-42

Table 4-23

Modified AACI PeriphID3 register

4-43

Table 4-24

Character LCD display implementation

4-44

Table 4-25

Character LCD control and data registers

4-45

Table 4-26

Character LCD display commands

4-46

Table 4-27

CLCDC implementation

4-47

Table 4-28

PrimeCell CLCDC register differences

4-48

Table 4-29

Values for different display resolutions

4-48

Table 4-30

Assignment of display memory to R[7:0], G[7:0], and B[7:0]

4-49

Table 4-31

PL110 hardware playback mode

4-51

Table 4-32

DMAC implementation

4-52

Table 4-33

DMA channels

4-53

Table 4-34

DMA mapping register format

4-54

Table 4-35

Ethernet implementation

4-55

x

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ARM DUI 0224I

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ARM ARM DUI 0224I manual Sysmisc