ARM ARM DUI 0224I

List of Tables

Table 4-36 GPIO implementation .............................................................................................. 4-56

Table 4-37 VIC Primary Interrupt Controller implementation ..................................................... 4-57

Table 4-38 SIC implementation ................................................................................................. 4-57

Table 4-39 Primary interrupt controller registers ....................................................................... 4-58

Table 4-40 Interrupt signals to primary interrupt controller ........................................................ 4-59

Table 4-41 Secondary interrupt controller registers .................................................................. 4-61

Table 4-42 Interrupt signals to secondary interrupt controller ................................................... 4-62

Table 4-43 KMI implementation ................................................................................................ 4-67

Table 4-44 MBX implementation ............................................................................................... 4-68

Table 4-45 MCI implementation ................................................................................................ 4-70

Table 4-46 MPMC implementation ............................................................................................ 4-71

Table 4-47 SDRAM register values ........................................................................................... 4-72

Table 4-48 PCI controller implementation ................................................................................. 4-74

Table 4-49 PCI bus memory map for AHB M2 bridge ............................................................... 4-75

Table 4-50 PCI controller registers ............................................................................................ 4-75

Table 4-51 PCI_IMAPx register format ..................................................................................... 4-77

Table 4-52 PCI_SELFID register format ................................................................................... 4-77

Table 4-53 PCI_FLAGS register format .................................................................................... 4-78

Table 4-54 PCI_SMAPx register format .................................................................................... 4-79

Table 4-55 PCI backplane configuration header addresses (self-config) .................................. 4-80

Table 4-56 PCI backplane configuration header addresses (normal configuration) .................. 4-80

Table 4-57 PCI configuration space header .............................................................................. 4-81

Table 4-58 PCI bus commands supported ................................................................................ 4-84

Table 4-59 RTC implementation ............................................................................................... 4-85

Table 4-60 Serial bus implementation ....................................................................................... 4-86

Table 4-61 Serial bus register ................................................................................................... 4-86

Table 4-62 Serial bus device addresses ................................................................................... 4-87

Table 4-63 SCI implementation ................................................................................................. 4-88

Table 4-64 SSP implementation ................................................................................................ 4-89

Table 4-65 SSMC implementation ............................................................................................ 4-91

Table 4-66 Register values for Intel flash, standard async read mode, no bursts ..................... 4-92

Table 4-67 Register values for Intel flash, async page mode ................................................... 4-92

Table 4-68 Register values for Samsung SRAM ....................................................................... 4-93

Table 4-69 Register values for Spansion BDS640 .................................................................... 4-93

Table 4-70 Register values for Spansion LV256 ....................................................................... 4-93

Table 4-71 System controller implementation ........................................................................... 4-95

Table 4-72 Timer implementation .............................................................................................. 4-96

Table 4-73 UART implementation ............................................................................................. 4-97

Table 4-74 USB implementation ............................................................................................... 4-99

Table 4-75 USB controller base address .................................................................................. 4-99

Table 4-76 VFP9 implementation ............................................................................................ 4-100

Table 4-77 Watchdog implementation ..................................................................................... 4-101

Table A-1 SSP signal assignment ............................................................................................. A-2

Table A-2 Smartcard connector signal assignment ................................................................... A-3

Table A-3 Signals on expansion connector ............................................................................... A-4

Table A-4 Serial plug signal assignment ................................................................................... A-5

Table A-5 Multimedia Card interface signals ............................................................................. A-9