ARM ARM DUI 0224I manual Interrupt signals to primary interrupt controller, VICINTSOURCE31

Programmer’s Reference

Table 4-39 Primary interrupt controller registers (continued)

Address	Name	Access	Description
0x10140300–	PICITCR,	Read/write	Test control registers
0x10140310	PICITIP1,
	PICITIP2,
	PICITOP1,
	PICITOP2,
0x10140FE0–	PICPeriphID0–	Read	Peripheral identification registers
0x10140FEC	PICPeriphID3
0x10140FF0–	PICPCellID0–	Read	PrimeCell identification registers
0x10140FFC	PICPCellID3

The bit assignments for the primary interrupt controller are shown in Figure 4-22 and Table 4-40. Each bit corresponds to an interrupt source. Use the bit to enable or disable the interrupt or to check the interrupt status.

		Figure 4-22 Primary interrupt registers
		Table 4-40 Interrupt signals to primary interrupt controller
Bit	Interrupt sourcea	Description
[31]	VICINTSOURCE31	External interrupt from secondary controller

[30]VICINTSOURCE30 External interrupt signal from RealView Logic Tile or PCI3 interrupt signal

[29]VICINTSOURCE29 External interrupt signal from RealView Logic Tile or PCI2 interrupt signal

[28]VICINTSOURCE28 External interrupt signal from RealView Logic Tile or PCI1 interrupt signal

[27]VICINTSOURCE27 External interrupt signal from RealView Logic Tile or PCI0 interrupt signal

ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved. 4-59