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ARM ARM DUI 0224I - page 107

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Hardware Description

ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved. 3-45

Figure 3-20 Clock sources for asynchronous AHB bridges

Contents

Main RealView Platform Baseboard for ARM926EJ-S User Guide Copyright 2003-2010 ARM Limited. All rights reserved. Page Page Contents RealView Platform Baseboard for ARM926EJ-S Chapter 4 Programmers Reference Appendix A Signal Descriptions Appendix B Specifications Appendix C CLCD Display and Adaptor Board Appendix D PCI Backplane and Enclosure Appendix E Memory Expansion Boards Page List of Tables RealView Platform Baseboard for ARM926EJ-S Page Page Page List of Figures RealView Platform Baseboard for ARM926EJ-S Page Page Page Page About this manual Page Page Page Page Page Page Feedback Page Page 1.1 About the PB926EJ-S Figure 1-1 PB926EJ-S layout L ine in (bottom) ine out (top) L Mic in MMC 0 (top) 1 (bottom) FPGA debug 1.2 PB926EJ-S architecture Page 1.2.1 System architecture Figure 1-2 shows the architecture of the PB926EJ-S. FPGA Figure 1-2 PB926EJ-S block diagram ARM926EJ-S Dev. Chip PB926EJ-S Page Page 1.3 Precautions Page Page 2.1 Setting up the RealView Platform 2.2 Setting the configuration switches Page 2.2.2 LED indicators Table2-3 lists the PB926EJ-S LED indicators and their function. Page Page 2.3 Connecting JTAG debugging equipment Page 2.4 Connecting the Trace Port Analyzer Page Page 2.5 Supplying power 2.6 Using the PB926EJ-S Boot Monitor and platform library Table2-4 lists the commands for the Boot Monitor. Table2-5 on page 2-16 lists the commands for the Configure subsystem. You must reset the board for the Boot Monitor Configure commands to take effect Table2-6 lists the commands for the Debug subsystem. Table2-7 lists the commands for the NOR Flash subsystem. Warning Page Page Page Page Page Page Page Page Page Chapter 3 Hardware Description Page 3.1 ARM926EJ-S PXP Development Chip Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 3.3 Reset controller Page Page Page Page Page Page 3.3.4 Reset signals Table3-4 describes reset signals. Page Page Page 3.4 Power supply control Page Page Page Page Page Figure 3-18 ARM926EJ-S PXP Development Chip internal multiplexors ARM926EJ-S Dev. Chip Flash SDRAM Table3-5 lists th e clock signals. Page Figure 3-19 Default clock sources and frequencies ARM926EJ-S Dev. Chip SDRAM FPGA Flash Page Page Page Page Page Page Page Page Page Page Page Page Page 3.6 Advanced Audio Codec Interface, AACI Page Page 3.7 Character LCD controller Page 3.8 CLCDC interface Page Page Page 3.9 DMA Page Page 3.10 Ethernet interface Page Page 3.11 GPIO interface Page Page Page 3.14 Memory Card Interface, MCI Page Page Page 3.15 PCI interface 3.16 Serial bus interface 3.17 Smart Card interface, SCI Page Page 3.18 Synchronous Serial Port, SSP Figure 3-36 SSP block diagram Page Page 3.19 User switches and LEDs 3.20 UART interface Figure 3-38 UARTs block diagram Figure 3-39 UART0 interface Page Page 3.21 USB interface The signals associated with the USB interfaces are shown in Table3-24. 3.22 Test, configuration, and debug interfaces Figure 3-42 Test and debug connectors, links, and LEDs Page Page Page Page Page Page Page Page Page Chapter 4 Programmers Reference Page 4.1 Memory map Page Page Page Page Page 4.2 Configuration and initialization Page Page Figure 4-2 Booting from NOR flash 1 Figure 4-3 Booting from static expansion memory Figure 4-4 Booting from AHB expansion Page Memory banks Table4-3 lists the controller memory banks, chip selects, and mem ory range. 4.3 Status and system control registers Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 4.4 AHB monitor 4.5 Advanced Audio CODEC Interface, AACI Page 4.6 Character LCD display The control and data registers for the character LCD interface are listed in Table4-25. An overview of the commands available is listed in Table4-26. . 4.7 Color LCD Controller, CLCDC Page Page Page Page 4.8 Direct Memory Access Controller and mapping registers Page Page 4.9 Ethernet 4.10 General Purpose Input/Output, GPIO Bit 7 of GPIO 3 is used for the battery voltage signal BATOK. 4.11 Interrupt controllers Page Page Page Page Page Page Page Example 4-2 Pseudo code for SIC SCI1 card out interrupt Example 4-3 shows clearing and re-enabling the SIC SCI1 card out interrupt by using PIC_SCR31. Example 4-3 Clearing and re-enabling SCI1 card out interrupt Page 4.12 Keyboard and Mouse Interface, KMI 4.13 MBX Page 4.15 MultiMedia Card Interfaces, MCIx 4.16 MultiPort Memory Controller, MPMC Page Page 4.17 PCI controller The PCI controller is implemented in the FPGA and controls the interface to the PCI bus. Caution Page Page Page Page Page Page or Page Page Page 4.18 Real Time Clock, RTC 4.19 Serial bus interface Page 4.20 Smart Card Interface, SCI 4.21 Synchronous Serial Port, SSP Page 4.22 Synchronous Static Memory Controller, SSMC Page Page Page 4.23 System Controller 4.24 Timers 4.25 UART Page 4.26 USB interface 4.27 Vector Floating Point, VFP9 4.28 Watchdog Page Appendix A Signal Descriptions A.1 Synchronous Serial Port interface Figure A-1 shows the signals on the expansion SSP interface connector J29. The signals associated with the SSP are shown in TableA-1. A.2 Smart Card interface Page A.3 UART interface A.4 USB interface A.5 Audio CODEC interface A.6 MMC and SD flash card interface Page A.7 CLCD display interface Page Figure A-9 CLCD Interface connector J18 A.8 VGA display interface A.9 GPIO interface Each data pin has an on-board 10K pullup resistor to 3.3V. Figure A-11 GPIO connector J15 GPIO0 and GPIO1 J16 GPIO2 and GPIO3 A.10 Keyboard and mouse interface The pinout of the KMI connectors J23 and J24 is shown in Figure A-12. TableA-8 shows signals on the KMI connectors. A.11 Ethernet interface LEDB Pin 1 LEDA A.12 RealView Logic Tile header connectors Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page B.1 Electrical specification Page Page B.2 Clock rate restrictions of 28.5ns). Page Page Page Page Page C.1 About the CLCD display and adaptor board Page Page Page C.2 Installing the CLCD display Page Page Page J2 Expansion connector (to development board) Figure C-6 CLCD buffer and power supply control links C.3 Touchscreen controller interface Figure C-7 Touchscreen and keypad interface Connector Interface socket J13 A/D and keypad connector Touch screen controller J8 J10 Y_POS Y_NEG X_POS X_NEG Touch screen resistive sheets Page Page C.4 Connectors Page Page Page Page Page Page D.1 Connecting the PB926EJ-S to the PCI enclosure Page Page Page PCI Backplane and Enclosure D-6 Copyright 2003-2010 ARM Limited. All rights reserved. ARM DUI 0224I 6mm D.2 Backplane hardware 50.6mm J4 Mictor DIP 171mm Page Page Page D.3 Connectors Page D.3.3 JTAG connector The signals on the JTAG connector J5 are shown in FigureD-6. Page E.1 About memory expansion Page Page Page E.3 EEPROM contents The base address of the information block is determined by the device chip select used. Page Page Page Page Page E.4 Connector pinout Page Page Page Page Page Page E.5 Mechanical layout Figure E-6 shows the dynamic memory expansion board (viewed from above). Figure E-7 Static memory board layout Figure E-6 Dynamic memory board layout Figure E-7 shows the static memory expansion board (viewed from above). Page F.1 About the RealView Logic Tile Page F.3 Header connectors Page Page Page Page Page FPGA Figure F-5 Clock signals and the RealView Logic Tile Clock generators and crystals ARM 926EJ-S Dev. Chip Clock select circuit Page Page FPGA Logic Tile Figure F-6 Bus signals for RealView Logic Tile and FPGA S S S M Page Appendix G Configuring the USB Debug Connection G.1 Installing the RealView ICE Micro Edition driver Page Page G.2 Changes to RealView Debugger G.3 Using the USB debug port to connect RealView Debugger Page Page Page G.4 Using the Debug tab of the RealView Debugger Register pane Page Page Page Page Index A B C D E F G I N P R S T U V W

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