ARM ARM DUI 0224I manual Table F-1 RealView Logic Tile clock signals

RealView Logic Tile

Ensure that your RealView Logic Tile configuration is compatible with the clock sources you are using on the PB926EJ-S. See RealView Logic Tile clocks on page 3-52 for more information on clock selection and routing.

			Table F-1 RealView Logic Tile clock signals
PB926EJ-S signal	RealView Logic Tile	Direction	Description
	signal (top header)
GLOBALCLK	CLK_GLOBAL	I/O	Global clock connected to all RealView Logic
			Tiles. Each tile and the PB926EJ-S can accept or
			generate the clock.
nGLOBALCLKEN	Z50	To VPB	If driven HIGH by the RealView Logic Tile, this
			signal disables the local source for GLOBALCLK
			on the PB926EJ-S and allows the RealView Logic
			Tile to supply GLOBALCLK. The signal is
			normally pulled LOW by a resistor to ground
			within the FPGA. The state of nGLOBALCLKEN
			can be read from the HCLKCTL[0] bit in the
			SYS_CONDATA1 register (see Configuration
			registers SYS_CFGDATAx on page 4-25).
HCLKM2F2L	ZU217	To tile	FPGA M2 clock to RealView Logic Tile.
NC	CLK_NEG_DN_IN	-	-
NC	CLK_POS_DN_IN	-	-
HCLKSF2L	CLK_NEG_UP_OUT	To tile	FPGA S clock to RealView Logic Tile.
HCLKM1F2L	CLK_POS_UP_OUT	To tile	FPGA M1 clock to RealView Logic Tile.
NC	CLK_UP_THRU	-	-
LT_SMCLK0	CLK_OUT_PLUS1	To tile	Static memory clock 0 to RealView Logic Tile.
LT_SMCLK1	CLK_OUT_PLUS2	To tile	Static memory clock 1 to RealView Logic Tile.
NC	CLK_IN_PLUS1	-	-
NC	CLK_IN_PLUS2	-	-
NC	CLK_DN_THRU	-	-
HCLKM1L2F	XU128	From tile	RealView Logic Tile clock to multiplexor that
			provides M1 clock for the FPGA.

F-8 Copyright © 2003-2010 ARM Limited. All rights reserved. ARM DUI 0224I