ARM ARM DUI 0224I 4.21 Synchronous Serial Port, SSP

Programmer’s Reference

4.21 Synchronous Serial Port, SSP

The PrimeCell Synchronous Serial Port (SSP) is an AMBA compliant SoC peripheral

that is developed, tested, and licensed by ARM Limited.

The SSP functions as a master or slave interface that enables synchronous serial

communication with slave or master peripherals having one of the following:

• a Motorola SPI-compatible interface

• a Texas Instruments synchronous serial interface

• a National Semiconductor Microwire interface.

In both master and slave configurations, the PrimeCell SSP performs:

• parallel-to-serial conversion on data written to a transmit FIFO

• serial-to-parallel conversion and FIFO buffering of received data.

Interrupts are generated to:

• request servicing of the transmit and receive FIFO

• inform the system that a receive FIFO over-run has occurred

• inform the system that data is present in the receive FIFO.

The SSP controller can be shared with the following resources:

• If the LCD adaptor board is fitted with a touch screen, the controller interfaces to

the SSP port to provide touch screen, keypad, LCD bias and analogue inputs. See

the LCD adaptor board TSCI appendix for further details.

Table4-64 SSP implementation

Property Value

Location ARM926EJ-S PXP Development Chip

Memory base address

0x101F4000

for SSP

Interrupt 11 on primary controller

DMA 9 for transmit 8 for receive

Release version ARM SSP PL022 r1p2

Reference documentation ARM PrimeCell Synchronous Serial Port Controller (PL022)

Technical Reference Manual (see also Synchronous Serial Port,

SSP on page 3-84)