ARM ARM DUI 0224I

Hardware Description

The configuration block in the development chip samples the state of the HDATAMx

pins while the rest of the chip is held in reset. The state of these pins is stored and used

to drive configuration signals within the chip and to define the operating mode of the

chip when reset is released. For more detail on the configuration signals, see

Configuration registers SYS_CFGDATAx on page 4-25 and the ARM926EJ-S

Development Chip Reference Manual.

Note

For details on configuring the clocks, see ARM926EJ-S PXP Development Chip clocks

on page 3-39.

Changing the ARM926EJ-S PXP Development Chip configuration at

runtime

To change the configuration of the ARM926EJ-S PXP Development Chip:

1. Program the appropriate values in the SYS_CFGDATAx registers, see

Configuration registers SYS_CFGDATAx on page 4-25.

2. Perform a configuration reset of the PB926EJ-S, but do not power-cycle, by

either:

• pressing the DEVCHIP RECONFIG pushbutton (next to the blue LED)

• programming the reset-depth register to level 2 (see Reset Control Register,

SYS_RESETCTL on page 4-31) and then performing a normal reset from

software, the reset pushbutton, or JTAG.

Restoring the default configuration

To restore the default processor configuration, power-cycle the PB926EJ-S or press the

FPGA CONFIG pushbutton (next to the yellow LED).

3.1.3 AHB bridges and the bus matrix

The ARM926EJ-S PXP Development Chip is based on the ARM926EJ-S PrimeXSys

Platform. The PrimeXSys Platform contains a multi-layer AHB bus matrix that routes

the signals from six masters to a number of slaves. These six masters are CPU-D,

CPU-I, DMA port0, DMA port1, CLCDC, Expansion master. The slaves include

internal AHB-APB bridges, the MPMC and SSMC memory controllers and three

expansion slaves, one of which is the internal AHB monitor block. (See Figure 3-1 on

page 3-4).