ARM ARM DUI 0224I manual DMA signals for external devices

Hardware Description

The names of DMA control signals change as they pass through the mapping logic in the FPGA. For the USB controller, DMACSREQ signals correspond to USBDREQ[1:0] and the DMACCLR signals correspond to USBDACK[1:0].

	Table 3-15 DMA signals for external devices
Signal	Description
DMACBREQ[5:0]	Burst request inputs to DMAC for channels 5 to 0.
DMACLBREQ[5:0]	Last burst request inputs to DMAC for channels 5 to 0.
DMACSREQ[5:0]	Single request inputs to DMAC for channels 5 to 0.
DMACLSREQ[5:0]	Last single request inputs to DMAC for channels 5 to 0.
DMACCLR[5:0]	Clear outputs from DMAC. These signals acknowledge the request
	from the corresponding DMASREQ or DMABREQ signals.
DMACTC[5:0]	Terminal count outputs from DMAC.

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