ARM ARM DUI 0224I RealView Logic Tile clocks, Globalclk selection, XTALCLK/GLOBALCLK driven by

Hardware Description

3.5.2RealView Logic Tile clocks

The PB926EJ-S can be expanded by adding RealView Logic Tiles. The HCLKCTRL[0] signal (SYS_CONFIGDATA1[16]) indicates the state of the nGLOBALCLKEN signal that selects the source for GLOBALCLK (see Table 3-10).

	Table 3-10 GLOBALCLK selection
HCLKCTRL[0]	XTALCLK/GLOBALCLK driven by:
0	XTALCLKDRV signal from FPGA (from OSC0).
	This is the default.
1	GLOBALCLK signal from RealView Logic Tile
	(nGLOBALCLKEN pulled HIGH by the
	RealView Logic Tile)

See Appendix F RealView Logic Tile for details on tile clocks.

Caution

By default, the clock multiplexors select XTALCLKDRV from the FPGA (buffered version of OSC0 output) as the reference clock.

Setting Z50 HIGH on the RealView Logic Tile pulls nGLOBALCLKEN HIGH and selects the RealView Logic Tile as the source for the global clock and the AHB bridge clocks. However, you must ensure that you implement appropriate clock generation and selection logic in your RealView Logic Tile and that the clocks operate correctly at power on.

The RealView Logic Tile can also be selected to provide the external bridge clocks when an AHB bridge is operating in asynchronous mode. See Operating the AHB bridges in asynchronous mode on page 3-44 for more details.

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