ARM ARM DUI 0224I manual PCISMAPx registers

Programmer’s Reference

Figure 4-27 PCI_FLAGS register

Table 4-53 PCI_FLAGS register format

Bits Description

[31:2] Reserved.

[1]Target abort flag. The bit value is the same as bit 38 of the Command Status Register in the Xilinx PCI controller. This bit position is reserved for future use.

[0]Master abort flag. The bit value is the same as bit 39 of the Command Status Register in the Xilinx PCI controller. This bit will be HIGH if an error occurred while the PB926EJ-S was operating as a master.

PCI_SMAPx registers

The map registers provide memory address bits [31:28] of the AHB bus for PCI accesses as shown in Figure 4-28 on page 4-79. In this example, PCI_SMAP2 contains 0x2 and this is used for the high bits for the AHB S address bus.

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