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ARM ARM DUI 0224I manual Locating the self-config header table

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Programmer’s Reference

Locating the self-config header table

The slot positions for PCI cards are numbered from 11 to 31. The numbering is based on the address bit that is connected to the IDSEL line. The base address for the PCI configuration header is determined as follows:

0x41000000 + ((slot position)<<11)

For example, if the PB926EJ-S is put into slot C where PCI address bit 29 is connected to the IDSEL signal, then the base address for the PB926EJ-S header table is at memory location:

0x41000000 + (29<<11) = 0x4100E800

The self-configuration addresses for the slot A, B, and C in the PCI backplane are listed in Table 4-55.

Table 4-55 PCI backplane configuration header addresses (self-config)

		Address	Configuration header
	Slot	connected	Configuration header
	Slot	connected	memory
		to IDSEL	memory
		to IDSEL

	C	29	0x4100E800–0x4100E83F

	B	30	0x4100F000–0x4100F03F

	A	31	0x4100F800–0x4100F83F

The base address for normal configuration is 0x42000000. The normal configuration addresses for the slot A, B, and C in the PCI backplane are listed in Table 4-55.

Table 4-56 PCI backplane configuration header addresses (normal configuration)

		Address	Configuration header
	Slot	connected	Configuration header
	Slot	connected	memory
		to IDSEL	memory
		to IDSEL

	C	29	0x4200E800–0x4200E83F

	B	30	0x4200F000–0x4200F03F

	A	31	0x4200F800–0x4200F83F

4-80

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ARM DUI 0224I

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ARM ARM DUI 0224I manual Locating the self-config header table

Contents

RealView Platform Baseboard for ARM926EJ-S RealView Platform Baseboard for ARM926EJ-S User GuideCopyright 2003-2010 ARM Limited. All rights reserved Product Status Conformance Notices RealView Platform Baseboard for ARM926EJ-S User Guide Chapter Programmer’s Reference Appendix B Specifications Appendix G Configuring the USB Debug Connection List of Tables Sysmisc VFP9 implementation 100 Xii List of Figures Syssw Sysled Sysbootcs Sysmisc Figure D-4 Jtag signal flow on the PCI backplane Preface Feedback onProduct revision status Using this manualAbout this manual Intended audienceConventions TypographicalTiming diagrams Signals NumberingFurther reading ARM publicationsXxiii Other publications TFT-LCD Module LQ084V1DG21 Sharp Corporation, Osaka, JapanFeedback Feedback on this productFeedback on this manual Xxvi Introduction About the PB926EJ-S On page 1-3 shows the layout of the PB926EJ-SPB926EJ-S layout PB926EJ-S architecture Time of year clock with backup battery Field Programmable Gate-Array Fpga that implementsSystem architecture Shows the architecture of the PB926EJ-SDisplays 2 ARM926EJ-S PXP Development Chip3 PB926EJ-S Fpga RealView Logic Tile expansionMemory Clock generatorsDebug and test interfaces Precautions Ensuring safetyPreventing damage ARM DUI Getting Started Setting up the RealView Platform Setting the configuration switches Boot memory configurationSwitch Default Function in default position Selecting the boot deviceDefault switch positions S1-2 S1-1 DeviceLED Indicators LED indicatorsLists the PB926EJ-S LED indicators and their function Color Device FunctionLED ID Boot Monitor configuration Connecting Jtag debugging equipment Jtag connectionUSB debug port connection Connecting the Trace Port Analyzer Example of MultiTrace and Jtag connectionExample of RealView ICE and RealView Trace About using trace Trace connector and adaptor boardSupplying power Power connectorsUsing the PB926EJ-S Boot Monitor and platform library Running the Boot MonitorBoot Monitor commands Lists the commands for the Boot Monitor Boot Monitor commandsCommand Action Lists the commands for the Debug subsystem Boot Monitor Configure commandsBoot Monitor Debug commands Lists the commands for the NOR Flash subsystem Boot Monitor NOR flash commandsRebuilding the Boot Monitor Boot Monitor NOR flash commands CommandActionGetting Started Loading Boot Monitor into NOR flash For RealView DebuggerFrom the Debug menu → Include CommandsRedirecting character output to hardware devices Rebuilding the platform library Building an application with the platform library Loading and running an application from NOR flash Load region in flashUsing a boot script to run an image automatically ARM DUI Fpga on DMA onInterrupts on Hardware Description ARM926EJ-S PXP Development Chip 1 ARM926EJ-S PXP Development Chip overviewARM926EJ-S PXP Development Chip block diagram ARM926EJ-S CPU is a member of the ARM9 Thumb family. Embedded Trace Macrocell ETM provides signals for off-chipThis high-performance, low-power Vector Floating-Point VFP ARM926EJ-S r0p3 macrocell is a 32-bit cached processor withMemory controllers Configuration control Synchronous serial portConfiguration switches Configuration from the DEV Chip Reconfig pushbutton Configuration signals from SYSCFGDATAxRestoring the default configuration AHB bridges and the bus matrixSimultaneous access Example of multiple masters AHB map Core APB and DMA APB map Memory interface Memory devicesAHB monitor AHB monitor connectionFpga Shows the architecture of the Fpga on the PB926EJ-SFpga configuration For details on Fpga components, seeFpga image 1 this is the image supplied with the board Localdone Globaldone Hardware Description Reset controller Reset and reconfiguration logic11 PB926EJ-S reset logic Memory Reset levelDefault values Registers Peripherals12 Reset signal sequence See -4 on page 3-29 for a description of the reset signals 13 Programmable reset levelMemory aliasing at reset NSTATICCS1 if one of BOOTCSSEL10 is not b1114 Boot memory remap logic Reset signal descriptions Reset signalsDescribes reset signals Name FunctionNPLLRESET NPBRESETNPBSDCRECONFIG NPORESETUsbwakeup Reset timing 15 Power-on reset and configuration timingPower supply control 16 Standby switch and power-supply control Clock architecture Clock domains for the PB926EJ-S are shown in FigureClock domains for the PB926EJ-S are ARM926EJ-S PXP Development ChipTiming the Ethernet bus. HCLKM2 typically generated from Where it can be used as the CPU clock for low-power modeSignal nGLOBALCLKEN from Z50 on the Logic Tile indicates to Controller interface to the FpgaARM DUI 1 ARM926EJ-S PXP Development Chip clocks 18 ARM926EJ-S PXP Development Chip internal multiplexorsLists the clock signals HCLKM2, HCLKS, PLLCLKEXT, GLOBALCLK, Default operationXtalclkdrv Xtalclkext19 Default clock sources and frequencies Xtalclkext Example of changing the CPU and bus clock frequenciesOperating the AHB bridges in asynchronous mode 20 Clock sources for asynchronous AHB bridges HCLKM2M2F HCLKCTRL70HCLKM1M2F HCLKSMF2FHclkctrl signal HCLKM2 driven by Default value of HCLKCTRL70 is 0xE0Hclkctrl signal HCLKM1 driven by HCLKM1 selectionHclks selection Hclkctrl signal Hclks driven byICS307 programmable clock generators HCLKSL2S and HCLKSL2F from tileClcdclkext Selecting the low-frequency clocks in power-saving mode Selecting slow startPeripheral clocks RealView Logic Tile clocks 10 Globalclk selectionXTALCLK/GLOBALCLK driven by 22 Example of selecting a tile clock for the AHB S bridge Clock multiplexor logic 23 Clock multiplexors Advanced Audio Codec Interface, Aaci 12 Audio system specificationCharacteristic Value PCMNo link Passive microphone on CODECMIC1 and CODECMIC2 13 AC’97 audio debug signals on J45 Pin number Signal name DescriptionCharacter LCD controller 25 Character display Clcdc interface 26 Display interface Chip Reference Manual for interface details 14 Display interface signals Signal DescriptionDMA 27 DMA channels 15 DMA signals for external devices USBETHA82 Ethernet interfaceUSBETHD310 TPO+ , TPOAbout the Smsc LAN91C111 ARM DUI 29 Gpio block diagram Gpio interfaceInterrupts 30 External and internal interrupt sourcesHardware Description 31 KMI block diagram Keyboard/Mouse Interface, KMIMemory Card Interface, MCI 17 MMC/SD interface signalsSignal Widebus mode SD only MMC mode default MMC or SD operationCard insertion and removal Card interface description32 MMI interface CARDINx 18 MMC signalsMCIPWRx MCIxDAT30PCI interface 33 PCI bridge19 Serial bus addresses Slave address Slave device Bit 20 Serial bus signalsSerial bus interface SbsclSmart Card interface, SCI 35 SCI block diagram NSCICLKENx SCIDATAIN0, SCICLKIN0, and SCIDETECT0 signals.SCICLKINx SCICLKOUTx36 SSP block diagram Synchronous Serial Port, SSP22 SSP signal descriptions Name DescriptionARM DUI User switches and LEDs 37 Switch and LED interfaceUart interface 38 UARTs block diagram SERxRTS NDRVINEN0SERxTXD SERxDTR a23 Serial interface signal assignment 41 OTG243 block diagram USB interface24 USB interface signal assignment Signal name Direction DescriptionTest, configuration, and debug interfaces 42 Test and debug connectors, links, and LEDs Jtag debug normal mode Jtag and USB debug port supportJtag configuration mode Jtag signals 25 Jtag related signalsName Description Function Return TCK 25 Jtag related signals Name Description FunctionRtck NCFGENDbgack NRTCKEN43 Jtag connector signals 44 Jtag signal routing 45 RealView Logic Tile Jtag circuitry ChipScope integrated logic analyzer Embedded trace supportEthernet on MBX onTimers on Uart onMemory map Sdram4KB Memory map Peripheral Location Interrupt a PIC Address Region SIC SizeVectored Interrupt Controller PIC PICUart 0 Interface Dev. chip PIC PCI 2GBSIC ARM Data bus memory map Configuration and initialization Remapping of boot memoryEnable Sdram at Switch is ON, the corresponding Bootcssel signal is HighRemoving boot remapping and enabling Sdram at Simplified version of the remap logic is shown in -14 onProgrammer’s Reference Booting from NOR flash Booting from NOR flashBooting from static expansion memory Booting from static expansion memoryBooting from AHB expansion memory Booting from AHB expansionMemory characteristics Memory banks Status and system control registers Name Address Accessa Reset Description Level Register map for system control registers Applycfgword active ID Register, Sysid Switch Register, SysswID Register, Sysid bit assignment Bits Access Description Describes the PB926EJ-S ID Register assignmentLED Register, Sysled SysledOscillator registers, SYSOSCx Shows the bit assignment of the registersLock Register, Syslock Describes the PB926EJ-S Lock Register bit assignmentConfiguration registers SYSCFGDATAx 6 100Hz Counter, SYS100HZConfiguration register Bits Power-on Description Reset stateHigh CFGHCLKEXTDIVSEL20, clock control PLL feedback see ARM926EJ-S PXP Development Chip clocks onHIGH, then expansion memory is aliased to Flag and Nonvolatile Flag Registers Register name Address Access Reset by DescriptionFlag registers, SYSFLAGx and SYSNVFLAGx Flag and Nonvolatile Flag Set RegistersBits Access Description Reset Control Register, Sysresetctl11 Reset level control PCI Control Register, Syspcictl12 MCI control Flash Control Register, SysflashClcd Control Register, Sysclcd 13 Flash control14 Sysclcd 14 Sysclcd registerBoot Select Register, Sysbootcs 14 2.2 inch LCD Control Register Sysclcdser15 Sysclcdser register 16 Sysbootcs 16 Boot configuration switches16 24MHz Counter, SYS24MHZ Miscellaneous System Control Register, SysmiscPnINTA LOW Name Address Access Description DMA peripheral map registers, SYSDMAPSRxSYS DMAPSR1 = USB a Oscillator reset registers, SYSOSCRESETx 19 shows the bit assignment of the registers20 Oscillator test registers Name Address Access Description Oscillator test registers, SYSTESTOSCxProperty Value AHB monitor21 AHB monitor implementation DMAPrimeCell Modifications 22 Aaci implementationBit Access Description 23 Modified Aaci PeriphID3 registerCharacter LCD display 24 Character LCD display implementationCharrd CharcomChardat CharmaskAn overview of the commands available is listed in Table 26 Character LCD display commandsCommand Bit Description Pattern Color LCD Controller, Clcdc 27 Clcdc implementationChip Display resolutions and display memory organization28 PrimeCell Clcdc register differences VGASanyo 3.8in panel Qvga 10MHz, 0x2C2A Svga 800x600 on Svga 36MHz, 0x2CACEpson 2.2in panel Qcif 10MHz, 0x2C2A 320x240ARM DUI CLD21 CLD23CLD22 CLD20Direct Memory Access Controller and mapping registers 32 Dmac implementation33 shows the DMA channel allocation 33 DMA channels DMA Requester21 SYSDMAP0-2 mapping register format 34 DMA mapping register formatEthernet 35 Ethernet implementationGeneral Purpose Input/Output, Gpio 36 Gpio implementationGpio 38 SIC implementation Interrupt controllers37 VIC Primary Interrupt Controller implementation FpgaPrimary interrupt controller 38 SIC implementation PropertyValueDmana VICINTSOURCE31 40 Interrupt signals to primary interrupt controllerBit Interrupt source a Description External interrupt from secondary controllerPwrfail GNDMBX ClcdSecondary interrupt controller 42 Interrupt signals to secondary interrupt controller Bit Interrupt Description SourceHandling interrupts Example 4-1 Clearing and re-enabling SCI0 card out interrupt Example 4-2 Pseudo code for SIC SCI1 card out interrupt Example 4-3 Clearing and re-enabling SCI1 card out interruptSCI1IMSC SCI1CARDOUTIM Keyboard and Mouse Interface, KMI 43 KMI implementationKMI 13 MBX 44 MBX implementationMove video coprocessor MultiMedia Card Interfaces, MCIx 45 MCI implementationMultiPort Memory Controller, Mpmc Register values46 Mpmc implementation Mpmcclkout runs 47 Sdram register valuesAddress Register name Value Description Offset SDRAM32M16BRCX32+0x144 MPMCDynamicRasCas2 PCI controller 48 PCI controller implementationDmac Address Name Access Description Control registersPCIIMAPx registers Map register formats are shown in -25 and -54 on50 PCI controller registers Bits Description Pciselfid registerPciflags register 52 Pciselfid register formatPCISMAPx registers PCI configuration Map register format is shown in -29 and Table54 PCISMAPx register format Locating the self-config header table 57 PCI configuration space header Address Configuration word function Default Offset ValueConfiguring the PCI interface Limitations of the PCI interface Interrupt Acknowledge Ignored Not available Real Time Clock, RTC 59 RTC implementationSbcontrols 60 Serial bus implementation Property ValueSbcontrol SbcontrolcDynamic expansion E2PROM 63 SCI implementation ARM PrimeCell Synchronous Serial Port Controller PL022 Register, Sysclcd on Synchronous Static Memory Controller, Ssmc 65 Ssmc implementation67 Register values for Intel flash, async page mode Address Name of Ssmc Value Description Register68 Register values for Samsung Sram SMBCR4 SMBWSTOENR4SMBWSTWENR4 SMBWSTBRDR4System Controller See also Status and system control registers onTimers 72 Timer implementationUart 73 Uart implementationPrimeCell Modifications 74 USB implementation Address DescriptionVector Floating Point, VFP9 76 VFP9 implementationWatchdog 77 Watchdog implementation102 Signal Descriptions Signal name Description Signals associated with the SSP are shown in Table A-1Table A-1 SSP signal assignment Synchronous Serial Port interfacePin Signal Description Smart Card interfaceTable A-3 Signals on expansion connector Signal Pin Signal nameTop Bottom Table A-4 Serial plug signal assignmentPB926EJ-S provides four serial transceivers SER1DTR a SER2DTR a SER3DTR aFigure A-5 shows the USB connectors Figure A-6 Audio connectors Audio Codec interfaceMMC and SD flash card interface Figure A-7 MMC/SD card socket pin numberingTable A-5 lists the signal assignments Clle GND Clac Clcp Cllp Clfp Table A-6 Clcd Interface board connector J18 Pin SignalClcd display interface LCDID0LCDID2 ClpowerPWR3V5VSWITCH Vlcd Vddposswitch Vddnegswitch Tsmiso LCDID3 Tsmosi LCDID4 Lcdxwr GND LCDSD0 Lcdxrd LcdxcsFigure A-9 Clcd Interface connector J18 Table A-7 VGA connector signals Pin Description VGA display interfaceFigure A-11 Gpio connector Each data pin has an on-board 10KΩ pullup resistor toTable A-8 Mouse and keyboard port signal descriptions Keyboard KMI0, J24 Mouse KMI1, J23 Pin Signal FunctionKeyboard and mouse interface Signals on the Ethernet cable are shown in Table A-9 Table A-9 Ethernet signals Pin SignalPin RealView Logic Tile header connectors Figure A-14 HDRX, HDRY, and Hdrz upper pin numberingHdrx signals Table A-10 Hdrx J9 signals Platform signal Tile Pin SignalTable A-10 Hdrx J9 signals Platform signal Tile Pin SignalHCLKM1DRVL2S SmcancelwaitHBUSREQM2 HWRITEM2HDATAM29 HDATAM27HDATAM28 HDATAM210Hdry signals Table A-11 Hdry J12 signals Platform signal Tile signal Pin SignalHmastlocks HRESPS0Hreadys HselsHDATAS6 HDATAS5Ltclcp LtclleTable A-12 Hdrz J8 signals Platform signal Tile signal PinHdrz EXPSMADDR17 EXPSMADDR15EXPSMADDR16 EXPSMADDR18Table A-12 Hdrz J8 signals Platform signal Tile signal Pin HCLKM1RESF2L Clkposupout Ctdi BOOTCSSEL7 FpgaimageClknegdnin Dtdoin Dtdoout HCLKSRESF2L ClknegupoutEXPSMDATAS3 EXPSMDATAS1EXPSMDATAS2 EXPSMDATAS4EXPSMDATAS27 EXPSMDATAS26HBURSTM10 HPROTM13HADDRM120 HADDRM119HDATAM112 HDATAM111Figure A-15 Test points and debug connectors Test and debug connectionsJtag on page A-36 Test point Signal FunctionThis section contains the following subsections Overview of test pointsREFCLK1 SCIDATAOUTTDD0Intclk SPARE2Jtag USB debug portTrace connector pinout Table A-14 Trace connector J14 Channel PinFigure A-18 Embedded logic analyzer connector J33 Figure A-19 AMP Mictor connectorTable A-15 AHB monitor connector J17 Channel Pin Fpga debug connector pinout Table A-16 Fpga debug connector J39 Channel PinSpecifications Electrical specification Bus interface characteristicsTable B-1 shows the PB926EJ-S electrical characteristics Current requirements Powered from DCPowered from J34 or PCI bus Table B-2 Current requirements from DC System Typical MaxLoading on supply voltage rails Default clock rates for reliable operation are Clock rate restrictionsHwrite , HTRANS10 , HSIZE20 , HBURST20 , HRESETn inputAHB bus timing HTRANS10 , HSIZE20 , HBURST20 , and write dataMemory timing Peripheral timingClcdclk ScirefclkSspclk Mechanical details Figure B-1 shows the mechanical outline of the PB926EJ-SARM DUI Connectors on page C-15 Clcd Display and Adaptor BoardFigure C-1 Clcd adaptor board connectors bottom view About the Clcd display and adaptor boardFigure C-2 Small Clcd enclosure Figure C-3 Large Clcd enclosure Clcd Display and Adaptor Board Installing the Clcd display Figure C-5 Clcd adaptor board connectionTDK ConfigurationLCD power control CXA-L0612VJLSwitchedvddneg Switchedfixed Clpower Switchedvddpos SwitchedvddnegFixedswitch Invio Figure C-6 Clcd buffer and power supply control links VBAT21 Touchscreen controller interfaceTouchscreen interface architecture AUX21Touch SSP and Tsci Configuration Example C-1 SSP to Tsci interface setupTouchscreen controller programmer’s interface Example C-2 Configuring and reading the Tsci interface Connectors Interface connectorTable C-4 Clcd interface connector J2 Pin Signal LCD prototyping connector Table C-5 LCD prototyping connector J1 Signal PinTouchscreen prototyping connector Inverter prototyping connector5 A/D and keypad connector Table C-8 A/D and keypad J13 Signal PinAUX1 GND AUX2 VBAT1 VBAT2 Mechanical layout Figure C-9 Clcd adaptor board mechanical layoutARM DUI PCI Backplane and Enclosure Connecting the PB926EJ-S to the PCI enclosure PCI Backplane and Enclosure Setting the backplane configuration switches A socket, the socket is bypassed by an automatic switchConnecting two PB926EJ-S boards Figure D-2 Multiple boards on PCI busBackplane hardware Figure D-3 PCI backplaneCLK66ACTIVE Table D-1 LED indicatorsCLK33ACTIVE CLK133ACTIVETable D-3 Power and reset switches Table D-2 Configuration switchesSwitch Signal Description Test point Signal DescriptionFigure D-4 Jtag signal flow on the PCI backplane 3V3 12V Power connectorTable D-5 ATX power connector Signal Pin NPSONLogic analyzer connector Table D-6 Mictor connector pinoutChannel Pin Table D-6 Mictor connector pinout Channel Pin Jtag connectorSignals on the Jtag connector J5 are shown in Figure D-6 SPARE4Memory Expansion Boards Figure E-1 Dynamic memory board block diagram About memory expansionMemory board configuration Operation without expansion memoryMemory width selection on the static memory board Table E-1 Memory width encodingWidth Figure E-3 Memory board installation locations Fitting a memory boardEeprom contents Table E-2 Chip Select information block Function Address Value OffsetAddress Contents Offset Figure E-4 Chip select information blockEXPnCS memory device string CS6 access time in 0.1ps LSB Address Contents Example contents DYCS3 memory size in bytes Connector pinout Expansion connectorDATA2 DATA0DATA1 DATA3ADDR0 ADDR1ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 NRAS Table E-6 Static memory connector signalsPin No Signal NCASTable E-6 Static memory connector signals Pin No Signal Vddio aNCS3 ADDR2NCS4 NCS2NIRQ ADDR15 NCS0 ADDR16ADDR17 ADDR18Figure E-6 Dynamic memory board layout RealView Logic Tile About the RealView Logic Tile Fitting a RealView Logic Tile Figure F-2 RealView Logic Tile fitted on PB926EJ-SHeader connectors Variable I/O levels Figure F-3 HDRX, HDRY, and Hdrz upper pin numberingRealView Logic Tile I/O Figure F-4 RealView Logic Tile tristate for I/ORealView Logic Tile clocks Table F-1 RealView Logic Tile clock signals RealView Logic Tile ARM AHB buses used by the Fpga and RealView Logic Tiles AHB M1AHB S Example RealView Logic Tile implementationFigure F-6 Bus signals for RealView Logic Tile and Fpga Reset DnTRST pulseConfiguring the USB Debug Connection Installing the RealView ICE Micro Edition driver Installing the RealView Developer SuiteInstalling the RealView ICE Micro Edition driver on Windows Select Specify a locationConfiguring the USB Debug Connection Changes to RealView Debugger Figure G-1 Nodes added to Connection Control windowUsing the USB debug port to connect RealView Debugger Figure G-2 The Connection Control windowFigure G-3 ARM926EJ-S PXP Development Chip detected Figure G-5 Error shown when no devices are detected Configuring the USB Debug Connection Using the Debug tab of the RealView Debugger Register pane There are three groups of settingsTrue Global PropertiesFalse JtagclocktypeDevice Properties Semihosting Properties ARM DUI Jtag Uart AaciAHB MCILCD ReconfigDMA KMI LEDMove Uart SYS ResetctlTCM SCISSP Uart Xtalclkdrv