ARM ARM DUI 0224I manual Register values for Intel flash, async page mode

Programmer’s Reference

4.22.1Register values

Table 4-66 to Table 4-69 on page 4-93 lists the register values for the SSMC for typical operation of static memory devices and with a 35MHz system clock.

Note

The platform.a library contains memory setup routines. See Building an application with the platform library on page 2-23.

Table 4-66 Register values for Intel flash, standard async read mode, no bursts

Address		Name of SSMC	Value	Description
		register
+0xE0		SMBIDCYR7	0x0	Idle Cycle Control Register for bank 1
+0xE4		SMBWSTRDR7	0x4	Read Wait State Control Reg bank 1
+0xE8		SMBWSTWRR7	0x3	Write Wait State Control Reg Bank 1
+0xEc		SMBWSTOENR7	0x0	Output Enable Assertion Delay 1
+0xF0		SMBWSTWENR7	0x1	Write Enable Assertion Delay 1
+0xF4		SMBCR7	0x303021	Control Register for memory bank 1
+0xFC		SMBWSTBRDR7	0x0	Burst Read Wait state Control Reg 1
		Table 4-67 Register values for Intel flash, async page mode
	Address	Name of SSMC	Value	Description
		register
	+0xE0	SMBIDCYR7	0x0	Idle Cycle Control Register for bank 1
	+0xE4	SMBWSTRDR7	0x4	Read Wait State Control Reg bank 1
	+0xE8	SMBWSTWRR7	0x3	Write Wait State Control Reg Bank 1
	+0xEc	SMBWSTOENR7	0x0	Output Enable Assertion Delay 1
	+0xF0	SMBWSTWENR7	0x1	Write Enable Assertion Delay 1
	+0xF4	SMBCR7	0x303521	Control Register for memory bank 1
	+0xFC	SMBWSTBRDR7	0x0	Burst Read Wait state Control Reg 1

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