ARM ARM DUI 0224I Default operation, Xtalclkdrv, HCLKM2, HCLKS, PLLCLKEXT, GLOBALCLK, Xtalclkext

Hardware Description

Table 3-5 ARM926EJ-S PXP Development Chip clocks (continued)

Clock signal	Frequency	Description	Source
Peripheral clocks	24MHz and	The SSP, SCI, and UART use an external 24MHz as reference. The	24MHz
	1MHz	timers use an external 1MHZ clock as reference.	crystal
XTALCLKDRV	6–75MHz	For the default clock multiplexor setting, this signal is driven from	ICS307
		the FPGA (from OSC0) and is distributed as HCLKM1,	OSC0
		HCLKM2, HCLKS, PLLCLKEXT, GLOBALCLK, and
		XTALCLKEXT.
XTALCLKEXT	6–75MHz	When the ARM926EJ-S PXP Development Chip PLL is used, this	ICS307
		input is used as the reference clock for the PLL. When the on-chip	OSC0
		PLL is not used this input can be used as the reference clock for the
		CPU and AMBA clocks. This clock is selected by the Clock and
		Reset Controller which is controlled by the System Controller.

Default operation

Figure 3-19 on page 3-42 shows a simplified block diagram with default clock settings and the internal and external multiplexors replaced by an equivalent circuit.

Caution

It is recommended that you use the default value of 0xE0 for the clock multiplexing signals HCLKCTRL[7:0]. Changing the value of HCLKCTRL[7:0] is only required if you want to individually control the source for XTALCLKEXT (GLOBALCLK), AHB M1, AHB M2, or AHB S.

If you install a Logic Tile for example, you can add additional clock generation and control logic in the tile FPGA. If you change the multiplexing signals, ensure that you have programmed the oscillators to generate the correct bridge frequencies or have implemented the correct clock generation logic in your RealView Logic Tile.

ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved. 3-41