Manuals / ARM / Computer Equipment / Computer Hardware

ARM ARM DUI 0224I manual SYSDMAP0-2 mapping register format, DMA mapping register format

Models: ARM DUI 0224I

1 402

Download 402 pages 14.06 Kb

Page 220

Programmer’s Reference

		Figure 4-21 SYS_DMAP0-2 mapping register format
			Table 4-34 DMA mapping register format

Bit	Access	Description

[31:8]	-	Reserved

[7]	Read/write	Set to 1 to enable mapping

[6:5]	-	Reserved

[4:0]	Read/write	FPGA peripheral mapped to this channel
		b00000	= AACI Tx
		b00001	= AACI Rx
		b00010	= USB Aa
		b00011	= USB B
		b00100	= MCI 0
		b00101	= MCI 1
		b00110	= UART3 Tx
		b00111	= UART3 Rx
		b01000	= SCI0 int A
		b01001	= SCI0 int B

b01010–b11111 Reserved

a.The OTG243 controller provides three USB interfaces, OTG (USB1), USB2, USB3, and OTG. The OTG243, however, has only two DMA control channels, USB A and USB B, that are managed by the USBDACK[1:0] and USBDRQ[1:0] signals. To assign a DMA channel to a USB interface, both the DMA mapping register and the OTG243 must be programmed.

4-54

Copyright © 2003-2010 ARM Limited. All rights reserved.

ARM DUI 0224I

Image 220

ARM ARM DUI 0224I manual SYSDMAP0-2 mapping register format, DMA mapping register format

Contents

RealView Platform Baseboard for ARM926EJ-S User Guide RealView Platform Baseboard for ARM926EJ-SCopyright 2003-2010 ARM Limited. All rights reserved Product Status Conformance Notices RealView Platform Baseboard for ARM926EJ-S User Guide Chapter Programmer’s Reference Appendix B Specifications Appendix G Configuring the USB Debug Connection List of Tables Sysmisc VFP9 implementation 100 Xii List of Figures Syssw Sysled Sysbootcs Sysmisc Figure D-4 Jtag signal flow on the PCI backplane Preface Feedback onUsing this manual About this manualProduct revision status Intended audienceConventions TypographicalTiming diagrams Signals NumberingFurther reading ARM publicationsXxiii Other publications TFT-LCD Module LQ084V1DG21 Sharp Corporation, Osaka, JapanFeedback on this product FeedbackFeedback on this manual Xxvi Introduction About the PB926EJ-S On page 1-3 shows the layout of the PB926EJ-SPB926EJ-S layout PB926EJ-S architecture Time of year clock with backup battery Field Programmable Gate-Array Fpga that implementsSystem architecture Shows the architecture of the PB926EJ-S2 ARM926EJ-S PXP Development Chip 3 PB926EJ-S FpgaDisplays RealView Logic Tile expansionClock generators MemoryDebug and test interfaces Ensuring safety PrecautionsPreventing damage ARM DUI Getting Started Setting up the RealView Platform Setting the configuration switches Boot memory configurationSelecting the boot device Default switch positionsSwitch Default Function in default position S1-2 S1-1 DeviceLED indicators Lists the PB926EJ-S LED indicators and their functionLED Indicators Color Device FunctionLED ID Boot Monitor configuration Connecting Jtag debugging equipment Jtag connectionUSB debug port connection Connecting the Trace Port Analyzer Example of MultiTrace and Jtag connectionExample of RealView ICE and RealView Trace About using trace Trace connector and adaptor boardSupplying power Power connectorsRunning the Boot Monitor Using the PB926EJ-S Boot Monitor and platform libraryBoot Monitor commands Boot Monitor commands Lists the commands for the Boot MonitorCommand Action Boot Monitor Configure commands Lists the commands for the Debug subsystemBoot Monitor Debug commands Lists the commands for the NOR Flash subsystem Boot Monitor NOR flash commandsRebuilding the Boot Monitor Boot Monitor NOR flash commands CommandActionGetting Started Loading Boot Monitor into NOR flash For RealView DebuggerFrom the Debug menu → Include CommandsRedirecting character output to hardware devices Rebuilding the platform library Building an application with the platform library Loading and running an application from NOR flash Load region in flashUsing a boot script to run an image automatically ARM DUI DMA on Fpga onInterrupts on Hardware Description ARM926EJ-S PXP Development Chip 1 ARM926EJ-S PXP Development Chip overviewARM926EJ-S PXP Development Chip block diagram Embedded Trace Macrocell ETM provides signals for off-chip This high-performance, low-power Vector Floating-Point VFPARM926EJ-S CPU is a member of the ARM9 Thumb family. ARM926EJ-S r0p3 macrocell is a 32-bit cached processor withMemory controllers Configuration control Synchronous serial portConfiguration switches Configuration from the DEV Chip Reconfig pushbutton Configuration signals from SYSCFGDATAxRestoring the default configuration AHB bridges and the bus matrixSimultaneous access Example of multiple masters AHB map Core APB and DMA APB map Memory interface Memory devicesAHB monitor AHB monitor connectionFpga Shows the architecture of the Fpga on the PB926EJ-SFpga configuration For details on Fpga components, seeFpga image 1 this is the image supplied with the board Localdone Globaldone Hardware Description Reset controller Reset and reconfiguration logic11 PB926EJ-S reset logic Reset level Default valuesMemory Registers Peripherals12 Reset signal sequence See -4 on page 3-29 for a description of the reset signals 13 Programmable reset levelMemory aliasing at reset NSTATICCS1 if one of BOOTCSSEL10 is not b1114 Boot memory remap logic Reset signals Describes reset signalsReset signal descriptions Name FunctionNPBRESET NPBSDCRECONFIGNPLLRESET NPORESETUsbwakeup Reset timing 15 Power-on reset and configuration timingPower supply control 16 Standby switch and power-supply control Clock architecture Clock domains for the PB926EJ-S are shown in FigureClock domains for the PB926EJ-S are ARM926EJ-S PXP Development ChipWhere it can be used as the CPU clock for low-power mode Signal nGLOBALCLKEN from Z50 on the Logic Tile indicates toTiming the Ethernet bus. HCLKM2 typically generated from Controller interface to the FpgaARM DUI 1 ARM926EJ-S PXP Development Chip clocks 18 ARM926EJ-S PXP Development Chip internal multiplexorsLists the clock signals Default operation XtalclkdrvHCLKM2, HCLKS, PLLCLKEXT, GLOBALCLK, Xtalclkext19 Default clock sources and frequencies Xtalclkext Example of changing the CPU and bus clock frequenciesOperating the AHB bridges in asynchronous mode 20 Clock sources for asynchronous AHB bridges HCLKCTRL70 HCLKM1M2FHCLKM2M2F HCLKSMF2FDefault value of HCLKCTRL70 is 0xE0 Hclkctrl signal HCLKM1 driven byHclkctrl signal HCLKM2 driven by HCLKM1 selectionHclkctrl signal Hclks driven by ICS307 programmable clock generatorsHclks selection HCLKSL2S and HCLKSL2F from tileClcdclkext Selecting the low-frequency clocks in power-saving mode Selecting slow startPeripheral clocks 10 Globalclk selection RealView Logic Tile clocksXTALCLK/GLOBALCLK driven by 22 Example of selecting a tile clock for the AHB S bridge Clock multiplexor logic 23 Clock multiplexors 12 Audio system specification Characteristic ValueAdvanced Audio Codec Interface, Aaci PCMNo link Passive microphone on CODECMIC1 and CODECMIC2 13 AC’97 audio debug signals on J45 Pin number Signal name DescriptionCharacter LCD controller 25 Character display Clcdc interface 26 Display interface Chip Reference Manual for interface details 14 Display interface signals Signal DescriptionDMA 27 DMA channels 15 DMA signals for external devices Ethernet interface USBETHD310USBETHA82 TPO+ , TPOAbout the Smsc LAN91C111 ARM DUI 29 Gpio block diagram Gpio interfaceInterrupts 30 External and internal interrupt sourcesHardware Description 31 KMI block diagram Keyboard/Mouse Interface, KMI17 MMC/SD interface signals Signal Widebus mode SD only MMC mode defaultMemory Card Interface, MCI MMC or SD operationCard insertion and removal Card interface description32 MMI interface 18 MMC signals MCIPWRxCARDINx MCIxDAT30PCI interface 33 PCI bridge20 Serial bus signals Serial bus interface19 Serial bus addresses Slave address Slave device Bit SbsclSmart Card interface, SCI 35 SCI block diagram SCIDATAIN0, SCICLKIN0, and SCIDETECT0 signals. SCICLKINxNSCICLKENx SCICLKOUTx36 SSP block diagram Synchronous Serial Port, SSP22 SSP signal descriptions Name DescriptionARM DUI User switches and LEDs 37 Switch and LED interfaceUart interface 38 UARTs block diagram NDRVINEN0 SERxTXDSERxRTS SERxDTR a23 Serial interface signal assignment 41 OTG243 block diagram USB interface24 USB interface signal assignment Signal name Direction DescriptionTest, configuration, and debug interfaces 42 Test and debug connectors, links, and LEDs Jtag debug normal mode Jtag and USB debug port supportJtag configuration mode 25 Jtag related signals Jtag signalsName Description Function 25 Jtag related signals Name Description Function RtckReturn TCK NCFGENDbgack NRTCKEN43 Jtag connector signals 44 Jtag signal routing 45 RealView Logic Tile Jtag circuitry ChipScope integrated logic analyzer Embedded trace supportEthernet on MBX onTimers on Uart onSdram Memory map4KB Memory map Peripheral Location Interrupt a PIC Address Region SIC SizeVectored Interrupt Controller PIC PICUart 0 Interface Dev. chip PIC 2GB PCISIC ARM Data bus memory map Configuration and initialization Remapping of boot memorySwitch is ON, the corresponding Bootcssel signal is High Removing boot remapping and enabling Sdram atEnable Sdram at Simplified version of the remap logic is shown in -14 onProgrammer’s Reference Booting from NOR flash Booting from NOR flashBooting from static expansion memory Booting from static expansion memoryBooting from AHB expansion memory Booting from AHB expansionMemory characteristics Memory banks Status and system control registers Name Address Accessa Reset Description Level Register map for system control registers Applycfgword active Switch Register, Syssw ID Register, Sysid bit assignment Bits Access DescriptionID Register, Sysid Describes the PB926EJ-S ID Register assignmentLED Register, Sysled SysledOscillator registers, SYSOSCx Shows the bit assignment of the registersLock Register, Syslock Describes the PB926EJ-S Lock Register bit assignmentConfiguration registers SYSCFGDATAx 6 100Hz Counter, SYS100HZConfiguration register Bits Power-on Description Reset stateHigh CFGHCLKEXTDIVSEL20, clock control PLL feedback see ARM926EJ-S PXP Development Chip clocks onHIGH, then expansion memory is aliased to Register name Address Access Reset by Description Flag registers, SYSFLAGx and SYSNVFLAGxFlag and Nonvolatile Flag Registers Flag and Nonvolatile Flag Set RegistersReset Control Register, Sysresetctl 11 Reset level controlBits Access Description PCI Control Register, SyspcictlFlash Control Register, Sysflash Clcd Control Register, Sysclcd12 MCI control 13 Flash control14 Sysclcd 14 Sysclcd register14 2.2 inch LCD Control Register Sysclcdser Boot Select Register, Sysbootcs15 Sysclcdser register 16 Sysbootcs 16 Boot configuration switchesMiscellaneous System Control Register, Sysmisc 16 24MHz Counter, SYS24MHZPnINTA LOW DMA peripheral map registers, SYSDMAPSRx Name Address Access DescriptionSYS DMAPSR1 = USB a Oscillator reset registers, SYSOSCRESETx 19 shows the bit assignment of the registers20 Oscillator test registers Name Address Access Description Oscillator test registers, SYSTESTOSCxAHB monitor 21 AHB monitor implementationProperty Value DMAPrimeCell Modifications 22 Aaci implementationBit Access Description 23 Modified Aaci PeriphID3 registerCharacter LCD display 24 Character LCD display implementationCharcom ChardatCharrd Charmask26 Character LCD display commands An overview of the commands available is listed in TableCommand Bit Description Pattern Color LCD Controller, Clcdc 27 Clcdc implementationDisplay resolutions and display memory organization 28 PrimeCell Clcdc register differencesChip VGASvga 800x600 on Svga 36MHz, 0x2CAC Epson 2.2in panel Qcif 10MHz, 0x2C2ASanyo 3.8in panel Qvga 10MHz, 0x2C2A 320x240ARM DUI CLD23 CLD22CLD21 CLD20Direct Memory Access Controller and mapping registers 32 Dmac implementation33 shows the DMA channel allocation 33 DMA channels DMA Requester21 SYSDMAP0-2 mapping register format 34 DMA mapping register formatEthernet 35 Ethernet implementation36 Gpio implementation General Purpose Input/Output, GpioGpio Interrupt controllers 37 VIC Primary Interrupt Controller implementation38 SIC implementation Fpga38 SIC implementation PropertyValue Primary interrupt controllerDmana 40 Interrupt signals to primary interrupt controller Bit Interrupt source a DescriptionVICINTSOURCE31 External interrupt from secondary controllerGND MBXPwrfail ClcdSecondary interrupt controller 42 Interrupt signals to secondary interrupt controller Bit Interrupt Description SourceHandling interrupts Example 4-1 Clearing and re-enabling SCI0 card out interrupt Example 4-2 Pseudo code for SIC SCI1 card out interrupt Example 4-3 Clearing and re-enabling SCI1 card out interruptSCI1IMSC SCI1CARDOUTIM 43 KMI implementation Keyboard and Mouse Interface, KMIKMI 13 MBX 44 MBX implementationMove video coprocessor MultiMedia Card Interfaces, MCIx 45 MCI implementationRegister values MultiPort Memory Controller, Mpmc46 Mpmc implementation 47 Sdram register values Address Register name Value Description OffsetMpmcclkout runs SDRAM32M16BRCX32+0x144 MPMCDynamicRasCas2 48 PCI controller implementation PCI controllerDmac Address Name Access Description Control registersMap register formats are shown in -25 and -54 on PCIIMAPx registers50 PCI controller registers Pciselfid register Pciflags registerBits Description 52 Pciselfid register formatPCISMAPx registers Map register format is shown in -29 and Table PCI configuration54 PCISMAPx register format Locating the self-config header table 57 PCI configuration space header Address Configuration word function Default Offset ValueConfiguring the PCI interface Limitations of the PCI interface Interrupt Acknowledge Ignored Not available Real Time Clock, RTC 59 RTC implementation60 Serial bus implementation Property Value SbcontrolSbcontrols SbcontrolcDynamic expansion E2PROM 63 SCI implementation ARM PrimeCell Synchronous Serial Port Controller PL022 Register, Sysclcd on Synchronous Static Memory Controller, Ssmc 65 Ssmc implementation67 Register values for Intel flash, async page mode Address Name of Ssmc Value Description Register68 Register values for Samsung Sram SMBWSTOENR4 SMBWSTWENR4SMBCR4 SMBWSTBRDR4System Controller See also Status and system control registers onTimers 72 Timer implementationUart 73 Uart implementationPrimeCell Modifications 74 USB implementation Address DescriptionVector Floating Point, VFP9 76 VFP9 implementationWatchdog 77 Watchdog implementation102 Signal Descriptions Signals associated with the SSP are shown in Table A-1 Table A-1 SSP signal assignmentSignal name Description Synchronous Serial Port interfacePin Signal Description Smart Card interfaceTable A-3 Signals on expansion connector Signal Pin Signal nameTable A-4 Serial plug signal assignment PB926EJ-S provides four serial transceiversTop Bottom SER1DTR a SER2DTR a SER3DTR aFigure A-5 shows the USB connectors Figure A-6 Audio connectors Audio Codec interfaceMMC and SD flash card interface Figure A-7 MMC/SD card socket pin numberingTable A-5 lists the signal assignments Table A-6 Clcd Interface board connector J18 Pin Signal Clcd display interfaceClle GND Clac Clcp Cllp Clfp LCDID0Clpower PWR3V5VSWITCH Vlcd Vddposswitch VddnegswitchLCDID2 Tsmiso LCDID3 Tsmosi LCDID4 Lcdxwr GND LCDSD0 Lcdxrd LcdxcsFigure A-9 Clcd Interface connector J18 Table A-7 VGA connector signals Pin Description VGA display interfaceFigure A-11 Gpio connector Each data pin has an on-board 10KΩ pullup resistor toKeyboard KMI0, J24 Mouse KMI1, J23 Pin Signal Function Table A-8 Mouse and keyboard port signal descriptionsKeyboard and mouse interface Table A-9 Ethernet signals Pin Signal Signals on the Ethernet cable are shown in Table A-9Pin RealView Logic Tile header connectors Figure A-14 HDRX, HDRY, and Hdrz upper pin numberingHdrx signals Table A-10 Hdrx J9 signals Platform signal Tile Pin SignalTable A-10 Hdrx J9 signals Platform signal Tile Pin SignalSmcancelwait HBUSREQM2HCLKM1DRVL2S HWRITEM2HDATAM27 HDATAM28HDATAM29 HDATAM210Hdry signals Table A-11 Hdry J12 signals Platform signal Tile signal Pin SignalHRESPS0 HreadysHmastlocks HselsHDATAS5 LtclcpHDATAS6 LtcllePlatform signal Tile signal Pin Table A-12 Hdrz J8 signalsHdrz EXPSMADDR15 EXPSMADDR16EXPSMADDR17 EXPSMADDR18Table A-12 Hdrz J8 signals Platform signal Tile signal Pin Ctdi BOOTCSSEL7 Fpgaimage ClknegdninHCLKM1RESF2L Clkposupout Dtdoin Dtdoout HCLKSRESF2L ClknegupoutEXPSMDATAS1 EXPSMDATAS2EXPSMDATAS3 EXPSMDATAS4EXPSMDATAS26 HBURSTM10EXPSMDATAS27 HPROTM13HADDRM119 HDATAM112HADDRM120 HDATAM111Figure A-15 Test points and debug connectors Test and debug connectionsTest point Signal Function This section contains the following subsectionsJtag on page A-36 Overview of test pointsSCIDATAOUTTDD0 IntclkREFCLK1 SPARE2Jtag USB debug portTrace connector pinout Table A-14 Trace connector J14 Channel PinFigure A-18 Embedded logic analyzer connector J33 Figure A-19 AMP Mictor connectorTable A-15 AHB monitor connector J17 Channel Pin Fpga debug connector pinout Table A-16 Fpga debug connector J39 Channel PinSpecifications Bus interface characteristics Electrical specificationTable B-1 shows the PB926EJ-S electrical characteristics Powered from DC Powered from J34 or PCI busCurrent requirements Table B-2 Current requirements from DC System Typical MaxLoading on supply voltage rails Default clock rates for reliable operation are Clock rate restrictionsHRESETn input AHB bus timingHwrite , HTRANS10 , HSIZE20 , HBURST20 , HTRANS10 , HSIZE20 , HBURST20 , and write dataMemory timing Peripheral timingScirefclk ClcdclkSspclk Mechanical details Figure B-1 shows the mechanical outline of the PB926EJ-SARM DUI Connectors on page C-15 Clcd Display and Adaptor BoardFigure C-1 Clcd adaptor board connectors bottom view About the Clcd display and adaptor boardFigure C-2 Small Clcd enclosure Figure C-3 Large Clcd enclosure Clcd Display and Adaptor Board Installing the Clcd display Figure C-5 Clcd adaptor board connectionConfiguration LCD power controlTDK CXA-L0612VJLSwitchedvddneg Switchedvddneg Switchedfixed Clpower SwitchedvddposFixedswitch Invio Figure C-6 Clcd buffer and power supply control links Touchscreen controller interface Touchscreen interface architectureVBAT21 AUX21Touch Example C-1 SSP to Tsci interface setup SSP and Tsci ConfigurationTouchscreen controller programmer’s interface Example C-2 Configuring and reading the Tsci interface Interface connector ConnectorsTable C-4 Clcd interface connector J2 Pin Signal LCD prototyping connector Table C-5 LCD prototyping connector J1 Signal PinTouchscreen prototyping connector Inverter prototyping connectorTable C-8 A/D and keypad J13 Signal Pin 5 A/D and keypad connectorAUX1 GND AUX2 VBAT1 VBAT2 Mechanical layout Figure C-9 Clcd adaptor board mechanical layoutARM DUI PCI Backplane and Enclosure Connecting the PB926EJ-S to the PCI enclosure PCI Backplane and Enclosure Setting the backplane configuration switches A socket, the socket is bypassed by an automatic switchConnecting two PB926EJ-S boards Figure D-2 Multiple boards on PCI busBackplane hardware Figure D-3 PCI backplaneTable D-1 LED indicators CLK33ACTIVECLK66ACTIVE CLK133ACTIVETable D-2 Configuration switches Switch Signal DescriptionTable D-3 Power and reset switches Test point Signal DescriptionFigure D-4 Jtag signal flow on the PCI backplane Power connector Table D-5 ATX power connector Signal Pin3V3 12V NPSONTable D-6 Mictor connector pinout Logic analyzer connectorChannel Pin Jtag connector Signals on the Jtag connector J5 are shown in Figure D-6Table D-6 Mictor connector pinout Channel Pin SPARE4Memory Expansion Boards Figure E-1 Dynamic memory board block diagram About memory expansionMemory board configuration Operation without expansion memoryTable E-1 Memory width encoding Memory width selection on the static memory boardWidth Figure E-3 Memory board installation locations Fitting a memory boardEeprom contents Table E-2 Chip Select information block Function Address Value OffsetAddress Contents Offset Figure E-4 Chip select information blockEXPnCS memory device string CS6 access time in 0.1ps LSB Address Contents Example contents DYCS3 memory size in bytes Connector pinout Expansion connectorDATA0 DATA1DATA2 DATA3ADDR1 ADDR0ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 Table E-6 Static memory connector signals Pin No SignalNRAS NCASTable E-6 Static memory connector signals Pin No Signal Vddio aADDR2 NCS4NCS3 NCS2ADDR15 NCS0 ADDR16 ADDR17NIRQ ADDR18Figure E-6 Dynamic memory board layout RealView Logic Tile About the RealView Logic Tile Fitting a RealView Logic Tile Figure F-2 RealView Logic Tile fitted on PB926EJ-SHeader connectors Variable I/O levels Figure F-3 HDRX, HDRY, and Hdrz upper pin numberingRealView Logic Tile I/O Figure F-4 RealView Logic Tile tristate for I/ORealView Logic Tile clocks Table F-1 RealView Logic Tile clock signals RealView Logic Tile ARM AHB buses used by the Fpga and RealView Logic Tiles AHB M1AHB S Example RealView Logic Tile implementationFigure F-6 Bus signals for RealView Logic Tile and Fpga Reset DnTRST pulseConfiguring the USB Debug Connection Installing the RealView ICE Micro Edition driver Installing the RealView Developer SuiteInstalling the RealView ICE Micro Edition driver on Windows Select Specify a locationConfiguring the USB Debug Connection Changes to RealView Debugger Figure G-1 Nodes added to Connection Control windowUsing the USB debug port to connect RealView Debugger Figure G-2 The Connection Control windowFigure G-3 ARM926EJ-S PXP Development Chip detected Figure G-5 Error shown when no devices are detected Configuring the USB Debug Connection Using the Debug tab of the RealView Debugger Register pane There are three groups of settingsGlobal Properties FalseTrue JtagclocktypeDevice Properties Semihosting Properties ARM DUI Uart Aaci AHBJtag MCIReconfig DMA KMILCD LEDSYS Resetctl TCMMove Uart SCISSP Uart Xtalclkdrv