Hardware Description

3.3.2Reset level

Table 3-3 lists the default levels of reset that results from external sources.

Table 3-3 Reset sources and effects

 

 

 

FPGA reloaded

Dev. Chip

Reset

 

 

Hardware

reconfigured

generated

 

Reset

and Dev. Chip

External source

nBOARDPOR

from

for CPU,

level

configured with

 

generated

SYS_CFGDATA

memory and

 

 

default values

 

 

 

registers

peripherals

 

 

 

 

 

 

 

 

 

 

Power on

0

Yes

Yes

Yes

Yes

 

 

 

 

 

 

FPGA CONFIG

1

No

Yes

Yes

Yes

pushbutton

 

 

 

 

 

 

 

 

 

 

 

DEV CHIP RECONFIG

2

No

No

Yes

Yes

pushbutton

 

 

 

 

 

 

 

 

 

 

 

RESET pushbutton or

6

No

No

No

Yes

software reset

 

 

 

 

 

 

 

 

 

 

 

Figure 3-12 on page 3-25 shows the activity on the reset signals at different levels of reset.

The level of reset that results from pressing the RESET pushbutton or generating a software reset can be configured by the SYS_RESETCTL register (see also, Reset Control Register, SYS_RESETCTL on page 4-31). The ability to configure the reset level gives greater flexibility in designing applications, FPGA images, and Logic Tile IP.

Set SYS_RESETCTL[8] to generate a software reset.

The reset levels specified by SYS_RESETCTL[2:0] are:

b000 is reserved

b001 resets to level 1, CONFIGCLR

b010 resets to level 2, CONFIGINIT

b011 resets to level 3, DLLRESET (DLL located in FPGA)

b100 resets to level 4, PLLRESET (located in ARM926EJ-S PXP Development Chip)

b101 resets to level 5, PORESET

b110 resets to level 6, DOCRESET

b111 is reserved.

3-24

Copyright © 2003-2010 ARM Limited. All rights reserved.

ARM DUI 0224I

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ARM ARM DUI 0224I manual Reset level, Memory, Default values, Registers Peripherals