ARM ARM DUI 0224I manual Memory timing, Peripheral timing

Specifications

B.2.2 Memory timing

Table B-6 shows the memory timing. For more detail on timing and example waveforms, see the ARM PrimeCell Static Memory Controller (PL093) Technical Reference Manual and the ARM PrimeCell Multiport Memory Controller (GX175) Technical Reference Manual.)

Table B-6 ARM926EJ-S PXP Development Chip memory timing

Memory signals		Clock	tov	toh	tis	tih
SSMC outputs (SMDATA[31:0] for write,		SMCLK	10ns	1ns	-	-
nSMDATAEN[3:0], SMADDR[25:0], SMCS[7:0],
nSMOEN, nSMWEN, nSMBLS[3:0], and
CANCELSMWAIT)
SMCLK is typically 35MHz for a tcyc of 28.6ns.
SSMC inputs in asynchronous mode (SMDATA[31:0] for read,		SMCLK	-	-	5ns	1ns
SMWAIT, and CANCELSMWAIT)
SSMC inputs in synchronous mode (SMDATA[31:0] for read,		SMFBCLK	-	-	5ns	1ns
SMWAIT, and CANCELSMWAIT)
	Note
The SMFBCLK delay from SMCLK must be less than 1.5ns.
MPMC outputs (MPMCADDROUT[27:0],		MPMCCLK	4ns	0.5ns	-	-
MPMCCKEOUT[3:0], MPMCDQMOUT[3:0],
nMPMCOEOUT, nMPMCRASOUT, nMPMCRPOUT,
nMPMCWEOUT, MPMCDATA[31:0] for write )
MPMCCLK is typically 70MHz for a tcyc of 14.3ns.
MPMC inputs (MPMCFBCLKIN[3:0],		MPMCFBCLK	-	-	1ns	0.5ns
MPMCTESTREQA, for read)
	Note
The MPMCFBCLK delay from MPMCCLK must be less
than 1.5ns.

B.2.3 Peripheral timing

Table B-7 on page B-8 shows the peripheral and controller timing. For more detail on timing and example waveforms, see the relevant Technical Reference Manual for the module.

ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved. B-7