RealView Logic Tile header connectors | ARM ARM DUI 0224I manual

Signal Descriptions

A.12 RealView Logic Tile header connectors

Figure A-14 shows the pin numbers and power-blade usage of the HDRX, HDRY, and HDRZ headers on the PB926EJ-S.

Figure A-14 HDRX, HDRY, and HDRZ (upper) pin numbering

Caution

The I/O voltage on some pins of RealView Logic Tiles can be programmed by changing resistors on the tile. Signals between RealView Logic Tiles can be altered safely if both the sending and receiving tile use the same voltage.

However, all signals from the tile mounted on the expansion headers and the PB926EJ-Smust use 3.3V I/O levels.

All signals from the PB926EJ-S to the tile use 3.3V I/O levels. The 5V supply on the headers is to power voltage converters that might be present on the expansion tile.

HDRX (J9) signals on page A-18,HDRY (J12) signals on page A-22, and HDRZ (J8) signals on page A-26 list the signals on each header pin. See Appendix F RealView Logic Tile and the ARM LT-XC2V4000+ RealView Logic Tile User Guide for more information on RealView Logic Tile signals.

ARM DUI 0224I

Copyright © 2003-2010 ARM Limited. All rights reserved.

A-17

Image 285

ARM ARM DUI 0224I manual RealView Logic Tile header connectors, Figure A-14 HDRX, HDRY, and Hdrz upper pin numbering

Contents

RealView Platform Baseboard for ARM926EJ-S RealView Platform Baseboard for ARM926EJ-S User GuideCopyright 2003-2010 ARM Limited. All rights reserved Product Status Conformance Notices RealView Platform Baseboard for ARM926EJ-S User Guide Chapter Programmer’s Reference Appendix B Specifications Appendix G Configuring the USB Debug Connection List of Tables Sysmisc VFP9 implementation 100 Xii List of Figures Syssw Sysled Sysbootcs Sysmisc Figure D-4 Jtag signal flow on the PCI backplane Feedback on Preface About this manual Using this manualProduct revision status Intended audience Typographical Conventions Timing diagrams Numbering Signals ARM publications Further reading Xxiii TFT-LCD Module LQ084V1DG21 Sharp Corporation, Osaka, Japan Other publications Feedback Feedback on this productFeedback on this manual Xxvi Introduction On page 1-3 shows the layout of the PB926EJ-S About the PB926EJ-S PB926EJ-S layout PB926EJ-S architecture Field Programmable Gate-Array Fpga that implements Time of year clock with backup battery Shows the architecture of the PB926EJ-S System architecture 3 PB926EJ-S Fpga 2 ARM926EJ-S PXP Development ChipDisplays RealView Logic Tile expansion Memory Clock generatorsDebug and test interfaces Precautions Ensuring safetyPreventing damage ARM DUI Getting Started Setting up the RealView Platform Boot memory configuration Setting the configuration switches Default switch positions Selecting the boot deviceSwitch Default Function in default position S1-2 S1-1 Device Lists the PB926EJ-S LED indicators and their function LED indicatorsLED Indicators Color Device Function LED ID Boot Monitor configuration Jtag connection Connecting Jtag debugging equipment USB debug port connection Example of MultiTrace and Jtag connection Connecting the Trace Port Analyzer Example of RealView ICE and RealView Trace Trace connector and adaptor board About using trace Power connectors Supplying power Using the PB926EJ-S Boot Monitor and platform library Running the Boot MonitorBoot Monitor commands Lists the commands for the Boot Monitor Boot Monitor commandsCommand Action Lists the commands for the Debug subsystem Boot Monitor Configure commandsBoot Monitor Debug commands Boot Monitor NOR flash commands Lists the commands for the NOR Flash subsystem Boot Monitor NOR flash commands CommandAction Rebuilding the Boot Monitor Getting Started For RealView DebuggerFrom the Debug menu → Include Commands Loading Boot Monitor into NOR flash Redirecting character output to hardware devices Rebuilding the platform library Building an application with the platform library Load region in flash Loading and running an application from NOR flash Using a boot script to run an image automatically ARM DUI Fpga on DMA onInterrupts on Hardware Description 1 ARM926EJ-S PXP Development Chip overview ARM926EJ-S PXP Development Chip ARM926EJ-S PXP Development Chip block diagram This high-performance, low-power Vector Floating-Point VFP Embedded Trace Macrocell ETM provides signals for off-chipARM926EJ-S CPU is a member of the ARM9 Thumb family. ARM926EJ-S r0p3 macrocell is a 32-bit cached processor with Memory controllers Synchronous serial port Configuration control Configuration switches Configuration signals from SYSCFGDATAx Configuration from the DEV Chip Reconfig pushbutton AHB bridges and the bus matrix Restoring the default configuration Simultaneous access Example of multiple masters AHB map Core APB and DMA APB map Memory devices Memory interface AHB monitor connection AHB monitor Shows the architecture of the Fpga on the PB926EJ-S Fpga For details on Fpga components, see Fpga configuration Fpga image 1 this is the image supplied with the board Localdone Globaldone Hardware Description Reset and reconfiguration logic Reset controller 11 PB926EJ-S reset logic Default values Reset levelMemory Registers Peripherals 12 Reset signal sequence 13 Programmable reset level See -4 on page 3-29 for a description of the reset signals NSTATICCS1 if one of BOOTCSSEL10 is not b11 Memory aliasing at reset 14 Boot memory remap logic Describes reset signals Reset signalsReset signal descriptions Name Function NPBSDCRECONFIG NPBRESETNPLLRESET NPORESET Usbwakeup 15 Power-on reset and configuration timing Reset timing Power supply control 16 Standby switch and power-supply control Clock domains for the PB926EJ-S are shown in Figure Clock architecture ARM926EJ-S PXP Development Chip Clock domains for the PB926EJ-S are Signal nGLOBALCLKEN from Z50 on the Logic Tile indicates to Where it can be used as the CPU clock for low-power modeTiming the Ethernet bus. HCLKM2 typically generated from Controller interface to the Fpga ARM DUI 18 ARM926EJ-S PXP Development Chip internal multiplexors 1 ARM926EJ-S PXP Development Chip clocks Lists the clock signals Xtalclkdrv Default operationHCLKM2, HCLKS, PLLCLKEXT, GLOBALCLK, Xtalclkext 19 Default clock sources and frequencies Example of changing the CPU and bus clock frequencies Xtalclkext Operating the AHB bridges in asynchronous mode 20 Clock sources for asynchronous AHB bridges HCLKM1M2F HCLKCTRL70HCLKM2M2F HCLKSMF2F Hclkctrl signal HCLKM1 driven by Default value of HCLKCTRL70 is 0xE0Hclkctrl signal HCLKM2 driven by HCLKM1 selection ICS307 programmable clock generators Hclkctrl signal Hclks driven byHclks selection HCLKSL2S and HCLKSL2F from tile Clcdclkext Selecting slow start Selecting the low-frequency clocks in power-saving mode Peripheral clocks RealView Logic Tile clocks 10 Globalclk selectionXTALCLK/GLOBALCLK driven by 22 Example of selecting a tile clock for the AHB S bridge Clock multiplexor logic 23 Clock multiplexors Characteristic Value 12 Audio system specificationAdvanced Audio Codec Interface, Aaci PCM No link Passive microphone on CODECMIC1 and CODECMIC2 Pin number Signal name Description 13 AC’97 audio debug signals on J45 Character LCD controller 25 Character display Clcdc interface 26 Display interface Chip Reference Manual for interface details Signal Description 14 Display interface signals DMA 27 DMA channels 15 DMA signals for external devices USBETHD310 Ethernet interfaceUSBETHA82 TPO+ , TPO About the Smsc LAN91C111 ARM DUI Gpio interface 29 Gpio block diagram 30 External and internal interrupt sources Interrupts Hardware Description Keyboard/Mouse Interface, KMI 31 KMI block diagram Signal Widebus mode SD only MMC mode default 17 MMC/SD interface signalsMemory Card Interface, MCI MMC or SD operation Card interface description Card insertion and removal 32 MMI interface MCIPWRx 18 MMC signalsCARDINx MCIxDAT30 33 PCI bridge PCI interface Serial bus interface 20 Serial bus signals19 Serial bus addresses Slave address Slave device Bit Sbscl Smart Card interface, SCI 35 SCI block diagram SCICLKINx SCIDATAIN0, SCICLKIN0, and SCIDETECT0 signals.NSCICLKENx SCICLKOUTx Synchronous Serial Port, SSP 36 SSP block diagram Name Description 22 SSP signal descriptions ARM DUI 37 Switch and LED interface User switches and LEDs Uart interface 38 UARTs block diagram SERxTXD NDRVINEN0SERxRTS SERxDTR a 23 Serial interface signal assignment USB interface 41 OTG243 block diagram Signal name Direction Description 24 USB interface signal assignment Test, configuration, and debug interfaces 42 Test and debug connectors, links, and LEDs Jtag and USB debug port support Jtag debug normal mode Jtag configuration mode Jtag signals 25 Jtag related signalsName Description Function Rtck 25 Jtag related signals Name Description FunctionReturn TCK NCFGEN NRTCKEN Dbgack 43 Jtag connector signals 44 Jtag signal routing 45 RealView Logic Tile Jtag circuitry Embedded trace support ChipScope integrated logic analyzer MBX on Ethernet on Uart on Timers on Memory map Sdram4KB Peripheral Location Interrupt a PIC Address Region SIC Size Memory map PIC Vectored Interrupt Controller PIC Uart 0 Interface Dev. chip PIC PCI 2GBSIC ARM Data bus memory map Remapping of boot memory Configuration and initialization Removing boot remapping and enabling Sdram at Switch is ON, the corresponding Bootcssel signal is HighEnable Sdram at Simplified version of the remap logic is shown in -14 on Programmer’s Reference Booting from NOR flash Booting from NOR flash Booting from static expansion memory Booting from static expansion memory Booting from AHB expansion Booting from AHB expansion memory Memory characteristics Memory banks Status and system control registers Name Address Accessa Reset Description Level Register map for system control registers Applycfgword active ID Register, Sysid bit assignment Bits Access Description Switch Register, SysswID Register, Sysid Describes the PB926EJ-S ID Register assignment Sysled LED Register, Sysled Shows the bit assignment of the registers Oscillator registers, SYSOSCx Describes the PB926EJ-S Lock Register bit assignment Lock Register, Syslock 6 100Hz Counter, SYS100HZ Configuration registers SYSCFGDATAx Bits Power-on Description Reset state Configuration register High PLL feedback see ARM926EJ-S PXP Development Chip clocks on CFGHCLKEXTDIVSEL20, clock control HIGH, then expansion memory is aliased to Flag registers, SYSFLAGx and SYSNVFLAGx Register name Address Access Reset by DescriptionFlag and Nonvolatile Flag Registers Flag and Nonvolatile Flag Set Registers 11 Reset level control Reset Control Register, SysresetctlBits Access Description PCI Control Register, Syspcictl Clcd Control Register, Sysclcd Flash Control Register, Sysflash12 MCI control 13 Flash control 14 Sysclcd register 14 Sysclcd Boot Select Register, Sysbootcs 14 2.2 inch LCD Control Register Sysclcdser15 Sysclcdser register 16 Boot configuration switches 16 Sysbootcs 16 24MHz Counter, SYS24MHZ Miscellaneous System Control Register, SysmiscPnINTA LOW Name Address Access Description DMA peripheral map registers, SYSDMAPSRxSYS DMAPSR1 = USB a 19 shows the bit assignment of the registers Oscillator reset registers, SYSOSCRESETx Oscillator test registers, SYSTESTOSCx 20 Oscillator test registers Name Address Access Description 21 AHB monitor implementation AHB monitorProperty Value DMA 22 Aaci implementation PrimeCell Modifications 23 Modified Aaci PeriphID3 register Bit Access Description 24 Character LCD display implementation Character LCD display Chardat CharcomCharrd Charmask An overview of the commands available is listed in Table 26 Character LCD display commandsCommand Bit Description Pattern 27 Clcdc implementation Color LCD Controller, Clcdc 28 PrimeCell Clcdc register differences Display resolutions and display memory organizationChip VGA Epson 2.2in panel Qcif 10MHz, 0x2C2A Svga 800x600 on Svga 36MHz, 0x2CACSanyo 3.8in panel Qvga 10MHz, 0x2C2A 320x240 ARM DUI CLD22 CLD23CLD21 CLD20 32 Dmac implementation Direct Memory Access Controller and mapping registers 33 DMA channels DMA Requester 33 shows the DMA channel allocation 34 DMA mapping register format 21 SYSDMAP0-2 mapping register format 35 Ethernet implementation Ethernet General Purpose Input/Output, Gpio 36 Gpio implementationGpio 37 VIC Primary Interrupt Controller implementation Interrupt controllers38 SIC implementation Fpga Primary interrupt controller 38 SIC implementation PropertyValueDmana Bit Interrupt source a Description 40 Interrupt signals to primary interrupt controllerVICINTSOURCE31 External interrupt from secondary controller MBX GNDPwrfail Clcd Secondary interrupt controller Bit Interrupt Description Source 42 Interrupt signals to secondary interrupt controller Handling interrupts Example 4-1 Clearing and re-enabling SCI0 card out interrupt Example 4-3 Clearing and re-enabling SCI1 card out interrupt Example 4-2 Pseudo code for SIC SCI1 card out interrupt SCI1IMSC SCI1CARDOUTIM Keyboard and Mouse Interface, KMI 43 KMI implementationKMI 44 MBX implementation 13 MBX Move video coprocessor 45 MCI implementation MultiMedia Card Interfaces, MCIx MultiPort Memory Controller, Mpmc Register values46 Mpmc implementation Address Register name Value Description Offset 47 Sdram register valuesMpmcclkout runs SDRAM32M16BRCX32 +0x144 MPMCDynamicRasCas2 PCI controller 48 PCI controller implementationDmac Control registers Address Name Access Description PCIIMAPx registers Map register formats are shown in -25 and -54 on50 PCI controller registers Pciflags register Pciselfid registerBits Description 52 Pciselfid register format PCISMAPx registers PCI configuration Map register format is shown in -29 and Table54 PCISMAPx register format Locating the self-config header table Address Configuration word function Default Offset Value 57 PCI configuration space header Configuring the PCI interface Limitations of the PCI interface Interrupt Acknowledge Ignored Not available 59 RTC implementation Real Time Clock, RTC Sbcontrol 60 Serial bus implementation Property ValueSbcontrols Sbcontrolc Dynamic expansion E2PROM 63 SCI implementation ARM PrimeCell Synchronous Serial Port Controller PL022 Register, Sysclcd on 65 Ssmc implementation Synchronous Static Memory Controller, Ssmc Address Name of Ssmc Value Description Register 67 Register values for Intel flash, async page mode 68 Register values for Samsung Sram SMBWSTWENR4 SMBWSTOENR4SMBCR4 SMBWSTBRDR4 See also Status and system control registers on System Controller 72 Timer implementation Timers 73 Uart implementation Uart PrimeCell Modifications Address Description 74 USB implementation 76 VFP9 implementation Vector Floating Point, VFP9 77 Watchdog implementation Watchdog 102 Signal Descriptions Table A-1 SSP signal assignment Signals associated with the SSP are shown in Table A-1Signal name Description Synchronous Serial Port interface Smart Card interface Pin Signal Description Signal Pin Signal name Table A-3 Signals on expansion connector PB926EJ-S provides four serial transceivers Table A-4 Serial plug signal assignmentTop Bottom SER1DTR a SER2DTR a SER3DTR a Figure A-5 shows the USB connectors Audio Codec interface Figure A-6 Audio connectors Figure A-7 MMC/SD card socket pin numbering MMC and SD flash card interface Table A-5 lists the signal assignments Clcd display interface Table A-6 Clcd Interface board connector J18 Pin SignalClle GND Clac Clcp Cllp Clfp LCDID0 PWR3V5VSWITCH Vlcd Vddposswitch Vddnegswitch ClpowerLCDID2 Tsmiso LCDID3 Tsmosi LCDID4 Lcdxwr GND LCDSD0 Lcdxrd Lcdxcs Figure A-9 Clcd Interface connector J18 VGA display interface Table A-7 VGA connector signals Pin Description Each data pin has an on-board 10KΩ pullup resistor to Figure A-11 Gpio connector Table A-8 Mouse and keyboard port signal descriptions Keyboard KMI0, J24 Mouse KMI1, J23 Pin Signal FunctionKeyboard and mouse interface Signals on the Ethernet cable are shown in Table A-9 Table A-9 Ethernet signals Pin SignalPin Figure A-14 HDRX, HDRY, and Hdrz upper pin numbering RealView Logic Tile header connectors Table A-10 Hdrx J9 signals Platform signal Tile Pin Signal Hdrx signals Platform signal Tile Pin Signal Table A-10 Hdrx J9 signals HBUSREQM2 SmcancelwaitHCLKM1DRVL2S HWRITEM2 HDATAM28 HDATAM27HDATAM29 HDATAM210 Hdry signals Platform signal Tile signal Pin Signal Table A-11 Hdry J12 signals Hreadys HRESPS0Hmastlocks Hsels Ltclcp HDATAS5HDATAS6 Ltclle Table A-12 Hdrz J8 signals Platform signal Tile signal PinHdrz EXPSMADDR16 EXPSMADDR15EXPSMADDR17 EXPSMADDR18 Table A-12 Hdrz J8 signals Platform signal Tile signal Pin Clknegdnin Ctdi BOOTCSSEL7 FpgaimageHCLKM1RESF2L Clkposupout Dtdoin Dtdoout HCLKSRESF2L Clknegupout EXPSMDATAS2 EXPSMDATAS1EXPSMDATAS3 EXPSMDATAS4 HBURSTM10 EXPSMDATAS26EXPSMDATAS27 HPROTM13 HDATAM112 HADDRM119HADDRM120 HDATAM111 Test and debug connections Figure A-15 Test points and debug connectors This section contains the following subsections Test point Signal FunctionJtag on page A-36 Overview of test points Intclk SCIDATAOUTTDD0REFCLK1 SPARE2 USB debug port Jtag Table A-14 Trace connector J14 Channel Pin Trace connector pinout Figure A-19 AMP Mictor connector Figure A-18 Embedded logic analyzer connector J33 Table A-15 AHB monitor connector J17 Channel Pin Table A-16 Fpga debug connector J39 Channel Pin Fpga debug connector pinout Specifications Electrical specification Bus interface characteristicsTable B-1 shows the PB926EJ-S electrical characteristics Powered from J34 or PCI bus Powered from DCCurrent requirements Table B-2 Current requirements from DC System Typical Max Loading on supply voltage rails Clock rate restrictions Default clock rates for reliable operation are AHB bus timing HRESETn inputHwrite , HTRANS10 , HSIZE20 , HBURST20 , HTRANS10 , HSIZE20 , HBURST20 , and write data Peripheral timing Memory timing Clcdclk ScirefclkSspclk Figure B-1 shows the mechanical outline of the PB926EJ-S Mechanical details ARM DUI Clcd Display and Adaptor Board Connectors on page C-15 About the Clcd display and adaptor board Figure C-1 Clcd adaptor board connectors bottom view Figure C-2 Small Clcd enclosure Figure C-3 Large Clcd enclosure Clcd Display and Adaptor Board Figure C-5 Clcd adaptor board connection Installing the Clcd display LCD power control ConfigurationTDK CXA-L0612VJL Switchedvddneg Switchedfixed Clpower Switchedvddpos SwitchedvddnegFixedswitch Invio Figure C-6 Clcd buffer and power supply control links Touchscreen interface architecture Touchscreen controller interfaceVBAT21 AUX21 Touch SSP and Tsci Configuration Example C-1 SSP to Tsci interface setupTouchscreen controller programmer’s interface Example C-2 Configuring and reading the Tsci interface Connectors Interface connectorTable C-4 Clcd interface connector J2 Pin Signal Table C-5 LCD prototyping connector J1 Signal Pin LCD prototyping connector Inverter prototyping connector Touchscreen prototyping connector 5 A/D and keypad connector Table C-8 A/D and keypad J13 Signal PinAUX1 GND AUX2 VBAT1 VBAT2 Figure C-9 Clcd adaptor board mechanical layout Mechanical layout ARM DUI PCI Backplane and Enclosure Connecting the PB926EJ-S to the PCI enclosure PCI Backplane and Enclosure A socket, the socket is bypassed by an automatic switch Setting the backplane configuration switches Figure D-2 Multiple boards on PCI bus Connecting two PB926EJ-S boards Figure D-3 PCI backplane Backplane hardware CLK33ACTIVE Table D-1 LED indicatorsCLK66ACTIVE CLK133ACTIVE Switch Signal Description Table D-2 Configuration switchesTable D-3 Power and reset switches Test point Signal Description Figure D-4 Jtag signal flow on the PCI backplane Table D-5 ATX power connector Signal Pin Power connector3V3 12V NPSON Logic analyzer connector Table D-6 Mictor connector pinoutChannel Pin Signals on the Jtag connector J5 are shown in Figure D-6 Jtag connectorTable D-6 Mictor connector pinout Channel Pin SPARE4 Memory Expansion Boards About memory expansion Figure E-1 Dynamic memory board block diagram Operation without expansion memory Memory board configuration Memory width selection on the static memory board Table E-1 Memory width encodingWidth Fitting a memory board Figure E-3 Memory board installation locations Eeprom contents Function Address Value Offset Table E-2 Chip Select information block Figure E-4 Chip select information block Address Contents Offset EXPnCS memory device string CS6 access time in 0.1ps LSB Address Contents Example contents DYCS3 memory size in bytes Expansion connector Connector pinout DATA1 DATA0DATA2 DATA3 ADDR0 ADDR1ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 Pin No Signal Table E-6 Static memory connector signalsNRAS NCAS Vddio a Table E-6 Static memory connector signals Pin No Signal NCS4 ADDR2NCS3 NCS2 ADDR17 ADDR15 NCS0 ADDR16NIRQ ADDR18 Figure E-6 Dynamic memory board layout RealView Logic Tile About the RealView Logic Tile Figure F-2 RealView Logic Tile fitted on PB926EJ-S Fitting a RealView Logic Tile Header connectors Figure F-3 HDRX, HDRY, and Hdrz upper pin numbering Variable I/O levels Figure F-4 RealView Logic Tile tristate for I/O RealView Logic Tile I/O RealView Logic Tile clocks Table F-1 RealView Logic Tile clock signals RealView Logic Tile ARM AHB M1 AHB buses used by the Fpga and RealView Logic Tiles Example RealView Logic Tile implementation AHB S Figure F-6 Bus signals for RealView Logic Tile and Fpga DnTRST pulse Reset Configuring the USB Debug Connection Installing the RealView Developer Suite Installing the RealView ICE Micro Edition driver Select Specify a location Installing the RealView ICE Micro Edition driver on Windows Configuring the USB Debug Connection Figure G-1 Nodes added to Connection Control window Changes to RealView Debugger Figure G-2 The Connection Control window Using the USB debug port to connect RealView Debugger Figure G-3 ARM926EJ-S PXP Development Chip detected Figure G-5 Error shown when no devices are detected Configuring the USB Debug Connection There are three groups of settings Using the Debug tab of the RealView Debugger Register pane False Global PropertiesTrue Jtagclocktype Device Properties Semihosting Properties ARM DUI AHB Uart AaciJtag MCI DMA KMI ReconfigLCD LED TCM SYS ResetctlMove Uart SCI Xtalclkdrv SSP Uart