ARM ARM DUI 0224I manual Clock multiplexor logic

Hardware Description

3.5.3Peripheral clocks

Table 3-11 lists the other memory and peripheral clocks on the PB926EJ-S.

For more detail on the clocking system, see the files in the Schematics directory of the CD supplied with the PB926EJ-S.

Table 3-11 PB926EJ-S clocks and clock control signals

Clock signal	Frequency	Description	Source
AACIBITCLK	12.288MHz	This is the synchronization clock from the audio CODEC. The	Crystal
		clock is an input to the AACI PrimeCell.	oscillator
CLCDCLKEXT	6–50MHz	The clock for PL110 CLCD Controller in the development chip	ICS307
		can be derived from this input.	OSC4
ETHLCLK	AHB M2	ETHLCLK is used to synchronize data transfers between the	HCLKM2
		external controller and the FPGA. (The Ethernet controller uses a	(typically
		25MHz crystal for clocking signals to and from the Ethernet	OSC0)
		connector.)
MPMCCLK[4:0]	-	The dynamic memory clocks from the MPMC in the development	MPMC
		chip. This is a buffered version of HCLK.	controller
PCICLK	-	This is the clock from the PCI backplane.
SCIREFCLKEXT	24MHz	The clock for PL131 SCI in the development chip can be derived	24MHz
		from this input. This is a buffered version of REFCLK24MHZ.	reference
SMCLK[2:0]	-	The static memory clocks from the SSMC in the development	SSMC
		chip. This is HCLK divided by 1, 2, or 3.	controller

3.5.4Clock multiplexor logic

Figure 3-23 on page 3-55 shows the clock multiplexor switches and the effect of the

HCLKCTRL[4:0] signals.

Note

The HCLKx_L2S and HCLKx_L2F clocks must be driven from the same reference source in the RealView Logic Tile. The HCLKx_F2S and HCLKx_F2F clocks are driven from the same source in the PB926EJ-S FPGA. Two signals are used for each clock for loading purposes and to allow for future expansion.

3-54 Copyright © 2003-2010 ARM Limited. All rights reserved. ARM DUI 0224I