ARM ARM DUI 0224I HCLKCTRL70, HCLKM1M2F, HCLKM2M2F, HCLKSMF2F, HCLKM1F2F, HCLKM2F2F, HCLKSF2F

Models: ARM DUI 0224I

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Hardware Description

Table 3-6 Asynchronous clock signals

Clock signal

Frequency

Description

Source

 

 

 

 

HCLKCTRL[7:0]

-

These signals control the multiplexor that selects clocks for the

FPGA

 

 

ARM926EJ-S PXP Development Chip.

 

 

 

 

 

HCLKM1M2F

-

These are FPGA input clocks (for M1, M2, and S) that can be

Clock

HCLKM2M2F

 

routed to HCLKxM2F and used as clocks for the M1, M2, and S

select

HCLKSMF2F

 

buses in the FPGA.

logic

 

 

 

 

HCLKM1F2F

-

These are FPGA output clocks (for M1, M2, and S) that can be used

Clock

HCLKM2F2F

 

as feedback signals to DLLs in the FPGA.

select

HCLKSF2F

 

 

logic

 

 

 

 

HCLKM1F2S

-

These are FPGA output clocks (for M1, M2, and S) that can be used

FPGA

HCLKM2F2S

 

as ARM926EJ-S PXP Development Chip reference clocks.

 

HCLKSF2S

 

 

 

 

 

 

 

HCLKM1F2L

-

These are FPGA output clocks (for M1, M2, and S) that can be used

FPGA

HCLKM2F2L

 

as RealView Logic Tile reference clocks. By default, these are

 

HCLKSF2L

 

driven by OSC0.

 

 

 

 

 

HCLKM1L2S

-

These are RealView Logic Tile output clocks (for M1, M2, and S)

RealView

HCLKM2L2S

 

that can be used as ARM926EJ-S PXP Development Chip

Logic Tile

HCLKSL2S

 

reference clocks.

 

 

 

 

 

HCLKM1L2F

-

These are RealView Logic Tile output clocks (for M1, M2, and S)

RealView

HCLKM2L2F

 

that can be used as clocks for buses in the FPGA.

Logic Tile

HCLKSL2F

 

 

 

 

 

 

 

ICS307 control

-

The signals ICS307_CLK, ICS307_DATA, and

 

signals

 

ICS307_STRB[4:0] clock data from the SYS_OSCx registers in

 

 

 

the FPGA to the programmable oscillators.

 

 

 

 

 

OSC0

 

For the image provided with the FPGA and the default

 

 

 

HCLKCTRL[7:0] value of 0xE0, programmable oscillator OSC0

 

 

 

is the source for the XTALCLKEXT, GLOBAL_CLK,

 

 

 

HCLKM1, HCLKM2, HCLKS, and PLLCLKEXT signals.

 

 

 

 

 

OSC1

 

Programmable oscillator OSC1 is the source for PLLCLKEXT

 

 

 

and can be selected as the source for the HCLKM1 signal.

 

 

 

 

 

OSC2

 

Programmable oscillator OSC2 can be used the source for the

 

 

 

HCLKM2 signal.

 

 

 

 

 

OSC3

 

Programmable oscillator OSC3 can be used the source for the

 

 

 

HCLKS signal.

 

 

 

 

 

 

 

 

 

3-46

Copyright © 2003-2010 ARM Limited. All rights reserved.

ARM DUI 0224I

Page 108
Image 108
ARM ARM DUI 0224I HCLKCTRL70, HCLKM1M2F, HCLKM2M2F, HCLKSMF2F, HCLKM1F2F, HCLKM2F2F, HCLKSF2F, HCLKM1F2S, HCLKM2F2S, OSC0