ARM ARM DUI 0224I

Hardware Description

For the default clock source and configuration values:

• OSC0 provides the XTALCLKEXT input clock for the PLL in the ARM926EJ-S

PXP Development Chip.

• The PLL output CPUCLK is used as the CPU core clock and as the input to the

HCLK divider.

•HCLK is CPUCLK divided by 1, 2, 3, or 4 depending on the value of

CFGHCLKDIVSEL[1:0]. HCLK is used as the SDRAM clock MPMCCLK,

and as the inputs to the MBX and SMC clock dividers.

•HCLKEXT is HCLK divided by 1 to 8 depending on the value of

CFGHCLKEXTDIVSEL[2:0]. HCLKEXT is the reference clock for the

external part of the AMBA bridges M1, M2, and S. This clock is the feedback

clock for the PLL, therefore the frequency of HCLKEXT is the same as that of

XTALCLKEXT.

Setting the clock frequencies involves trade-offs between CPU performance, bus

performance, MBX performance, and memory access time. The clocks must also be

within their operational limits, see Clock rate restrictions on page B-5.

The AHB bridges operate in synchronous mode by default. The internal part of the AHB

bridge is clocked by HCLK and external part of the bridge is clocked by HCLKEXT.

HCLKEXT is the feedback to the PLL, so the HCLKEXT frequency is the same as

the PLL reference frequency XTALCLKEXT.

CPUCLK is generated by multiplying the reference XTALCLKEXT by the

HCLKDIV and HCLKEXTDIV values. For example, if XTALCLKEXT is 20MHz,

HCLKDIV is 3, and HCLKDIV is 3, the frequency of CPUCLK is 20*3*3 or 180MHz.

Selecting the values for HCLKDIV and HCLKEXTDIV must result in values for

CPUCLK, HCLK and HCLKEXT that are within their maximum frequency ranges.

Example of changing the CPU and bus clock frequencies

Use the following steps to set the external AMBA bus clock to 35MHz, the CPUCLK

rate to 210MHz, and the internal AMBA bus and SDRAM frequency to 70MHz:

• The external AMBA bus clock is at the same frequency as the XTALCLKEXT

signal, so OSC0 must be set to 35MHz. This requires that the SYS_OSC0 register

is loaded with

b0000010110010100111

(

0x02CA7

This sets the Divide Select bits to

b000

(divide by 10), the Reference Divider bits

b0010110

(divide by 24), and the VCO Divider bits to

b010100111

(multiply by

175). See ICS307 programmable clock generators on page3-48 and Oscill ator

registers, SYS_OSCx on page4-23 for details on programming OSC0.